參數(shù)資料
型號(hào): PI4S813L
英文描述: Supervisory Circuits | 4.63V Reset Active High Supervisor
中文描述: 監(jiān)控電路| 4.63V之間復(fù)位高有效監(jiān)
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 398K
代理商: PI4S813L
2
PS8703 09/23/03
PI4S705, PI4S706x, PI4S707, PI4S708x, PI4S813L
μP Supervisor Circuts
Pin Name
Type
Description
Manual-Reset
: triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250μA
pull-up current and can be driven from a TTL or CMOS logic line as well as shorted to ground with a
switch.
Power Supply
Ground Reference
for all signals
Power-Fail Voltage Monitor Input
: When PFI is less than 1.25V, PFO goes low. Connect PFI to GND
or Vcc when not used.
Power-Fail Output
: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays
high.
Watchdog Input
: If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and
WDO goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the
watchdog feature. The internal watchdog timer clears whenever reset is asserted, WDI is three-stated,
or WDI sees a rising or falling edge.
No Connect
Reset Output pulses
: low for 200ms when triggered, and stays low whenever Vcc is below the reset
threshold. It remains low for 200ms after V
CC
rises above the reset threshold or MR goes from low to
high. A watchdog timeout will not trigger RESET unless WDO is connected to MR.
Watchdog Output
: pulls low when the internal watchdog timer finishes its 1.6sec count and does not
go high again until the watchdog is cleared. WDO also goes low during low-line conditions. Whenever
Vcc is below the reset threshold, WDO stays low; however, unlike RESET, WDO does not have mini-
mum pulse width. As soon as V
CC
rises above the reset threshold, WDO goes high with no delay.
The inverse of RESET
: active high. Whenever RESET is high, RESET is low.
MR
Input
V
CC
GND
Power
Ground
PFI
Input
PFO
Output
WDI
Input
NC
RESET
Output
WDO
Output
RESET
Output
Pin Descriptiom
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