參數(shù)資料
型號(hào): PHP125N06L
廠商: NXP Semiconductors N.V.
英文描述: TrenchMOS transistor Logic level FET(TrenchMOS 晶體管標(biāo)準(zhǔn)電平場(chǎng)效應(yīng)管)
中文描述: TrenchMOS場(chǎng)效應(yīng)晶體管邏輯電平(TrenchMOS晶體管標(biāo)準(zhǔn)電平場(chǎng)效應(yīng)管)
文件頁數(shù): 1/9頁
文件大?。?/td> 71K
代理商: PHP125N06L
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
PHP125N06LT, PHB125N06LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 55 V
’Trench’
technology
Very low on-state resistance
Fast switching
Stable off-state characteristics
High thermal cycling performance
Low thermal resistance
I
D
= 75 A
R
DS(ON)
8 m
(V
GS
= 5 V)
R
DS(ON)
7 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channelenhancement mode,logic level, field-effectpower transistor in aplastic envelopeusing ’
trench
’technology.
Thedevice has very low on-state resistance. Itis intended for use in dcto dc converters and general purpose switching
applications.
The PHP125N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB125N06LT is supplied in the SOT404 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage
I
D
Continuous drain current
CONDITIONS
T
j
= 25 C to 175C
T
j
= 25 C to 175C; R
GS
= 20 k
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
±
13
75
75
240
250
175
UNIT
V
V
V
A
A
A
W
C
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
I
DM
P
D
T
j
, T
stg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
d
g
s
1
3
tab
2
1 2 3
tab
March 1998
1
Rev 1.400
相關(guān)PDF資料
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