參數(shù)資料
型號(hào): PGA308AIDRKR
廠商: TEXAS INSTRUMENTS INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC10
封裝: 3 X 4 MM, GREEN, PLASTIC, SON-10
文件頁數(shù): 10/29頁
文件大小: 962K
代理商: PGA308AIDRKR
V
=
mux_sign
V + V
GI + V
GD
GO
OUT
IN
Coarse_Offset
Zero_DAC
[
]
?
(
SBOS440B – JULY 2008 – REVISED DECEMBER 2010
www.ti.com
OTP MEMORY BANKS
PGA308 TRANSFER FUNCTION
There are four one-time programmable (OTP) bank
Equation 1 shows the mathematical expression that is
selection registers: BANK SEL1, BANK SEL2, BANK
used to compute the output voltage, VOUT. This
SEL3, and BANK SEL4. Bank selection may be set
equation can also be rearranged algebraically to
four times by programming the BANK SELx registers
solve
for
different
terms.
For
example,
during
in order (1, 2, 3, 4). The default OTP bank used on
calibration, this equation is rearranged to solve for
POR is the location stored in the last programmed
VIN.
BANK SELx register. Therefore, if programmed,
BANK SEL4 always has priority over lower-numbered
(1)
bank select registers.
Where:
The PGA308 contains seven OTP user memory
mux_sign: This term changes the polarity of the
banks.
All
seven
of
these
banks
may
be
input signal; value is ±1
independently programmed. However, the default
bank at POR can be set only four times. The seven
VIN: The input signal for the PGA308; VIN1 = VINP,
possible OTP user memory banks allow an end
VIN2 = VINN
product with a microcontroller interface between the
VCoarse_Offset: The coarse offset DAC output
end-user and the PGA308 to select from up to seven
voltage
factory
pre-programmed
configurations.
It
also
GI: Input stage gain
provides
total
user
flexibility
for
any
other
VZero_DAC: Zero DAC output voltage
configuration through software communication over
the One-Wire interface (1W pin). This flexibility allows
GD: Gain DAC
no-scrap recovery from miscalibration situations.
GO: Output stage gain
18
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): PGA308
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