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參數(shù)資料
| 型號： | PGA103U |
| 英文描述： | KPT02A18-11PY |
| 中文描述： | 可編程增益放大器 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 119K |
| 代理商： | PGA103U |
6
PGA103
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the PGA103. Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the device pins as shown.
Some applications select gain of the PGA103 with switches
or jumpers. Figure 2 shows pull-up resistors connected to
assure a noise-free logic “1” when the switch or jumper is
off or open. Fixed-gain applications can connect the logic
inputs directly to V+ or ground (or other valid logic level)
without a series resistor.
OFFSET TRIMMING
Offset voltage is laser-trimmed to typically less than 200
μ
V
(referred to input) in all three gains. The input-referred offset
voltage can be different for each gain.
FIGURE 2. Switch or Jumper-Selected Gains.
Figure 3 shows a circuit used to trim the offset voltage of the
PGA103. An op amp buffers the trim voltage to provide a
low impedance at the ground terminal. This is required to
maintain accurate gain. Remember that the logic inputs, A
0
and A
1
, are referenced to this ground connection, so the
logic threshold voltage will be affected by the trim voltage.
This is insignificant if the offset adjustment is used only to
trim offset voltage. If a large offset is used (greater than
0.1V), be sure that the logic input signals provide valid logic
levels when referred to the voltage at the ground terminal,
pin 3.
NOTE: (1) Op amp buffer is required to preserve good gain accuracy—see
text.
FIGURE 3. Offset Voltage Trim Circuit.
GAIN
S
1
S
0
1
10
100
Closed Closed
Closed Open
Open Closed
Not Valid Open
Open
The input and output are referred to the ground terminal,
pin 3. This must be a low-impedance connection to assure
good gain accuracy. A resistance of 0.1
in series with the
ground pin will cause the gain in G=100 to decrease by
approximately 0.2%.
DIGITAL INPUTS
The digital inputs, A
0
and A
1
, select the gain according to
the logic table in Figure 1. The digital inputs interface
directly to common CMOS and TTL logic components. The
logic inputs are referenced to the ground terminal, pin 3.
The logic table in Figure 1 shows that logic “1” on both A
0
and A
1
is invalid. This logic code will not cause damage, but
the amplifier output will not be predictable while this code
is selected. The output will recover when a valid code is
selected.
The digital inputs are not latched, so a change in logic inputs
immediately selects a new gain. Switching time of the logic
is approximately 0.5
μ
s. The time to respond to gain change
is equal to the switching time plus the time it takes the
amplifier to settle to a new output voltage in the newly
selected gain (see settling time specifications).
Many applications use an external logic latch to access gain
control signals from a high speed data bus. Using an external
latch isolates the high speed digital bus from sensitive
analog circuitry. Locate the latch circuitry as far as practical
from analog circuitry to avoid coupling digital noise into the
analog circuitry.
FIGURE 1. Basic Connections.
NOTE: (1) Low impedance ground connection required for good gain
accuracy—see text.
Logic 0: (–5.6)
≤
V
≤
0.8V
Logic 1: 2V
≤
V
≤
(V+)
Logic voltages referred to pin 3.
A
0
A
1
PGA103
V+
100k
100k
2
1
3
7
4
V
IN
V
O
V+ V–
8
6
S
1
S
0
Logic threshold voltage
is altered by V
.
OK for V
TRIM
≤
100mV.
V
IN
V
O
= G (V
IN
– V
TRIM
)
2
1
3
V
TRIM
(1)
OPA602
100k
50k
33
±5mV
Trim Range
+15V
–15V
+15V –15V
A
1
PGA103
A
0
PGA103
V
IN
V
O
= G V
IN
V+
+15V
V–
–15V
2
1
3
7
8
6
4
1
10
100
Not Valid
0
0
1
1
0
1
0
1
GAIN
A
1
A
0
0.1μF
0.1μF
A
1
A
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PGA103U | 制造商:Texas Instruments 功能描述:IC PROGRAMMABLE GAIN AMPLIFIER 制造商:Texas Instruments 功能描述:IC, PROGRAMMABLE GAIN AMPLIFIER |
| PGA103U | 制造商:Texas Instruments 功能描述:PROGRAMMABLE GAIN AMPLIFIER IC |
| PGA103UE4 | 功能描述:特殊用途放大器 Programmable Gain Amplifier RoHS:否 制造商:Texas Instruments 通道數(shù)量:Single 共模抑制比（最小值）: 輸入補(bǔ)償電壓: 工作電源電壓:3 V to 5.5 V 電源電流:5 mA 最大功率耗散: 最大工作溫度:+ 70 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-20 封裝:Reel |
| PGA107M725C1-1251 | 制造商:MCKENZIE 功能描述: |
| PGA108M004B1-1205BLU | 制造商:FCI 功能描述: |
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