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參數(shù)資料
| 型號： | PG001M |
| 元件分類： | 運動控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, 0.015 A, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 213K |
| 代理商： | PG001M |
PG001M
PARALLEL-TO-SERIAL
DATA CONVERTER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Integra
ted
Cir
cuits
10
Figure 6 — A Latched Input-Bus Configuration
CLOCK
STROBE
SERIAL DATA
Dwg. EK-014-1
1
MODE SELECT
CCW/CW
RESET
VECTOR CONTROL
MODE SELECT2
MONITOR
CLOCK IN
P
PG001M
GND
V
DD
+5 V
LATCHES
(5)
GND
V
CC
STROBE
V
CC
A
B
At start-up, reseting the counter adds only another
clock interval (per figures 4 and 5). During high-speed
slewing, the
P is only occupied with sending clock
signals and monitoring the readback (MO). Hence, of a
200
s interval, with a slewing rate of 5 kHz, only 5 s is
required to provide the clock input. At slower, more
typical step rates, 5
s becomes an insignificant burden on
the
P controlling the stepping motor.
Other techniques to decrease and unburden the essen-
tial
P I/O lines and control logic are viable. Utilizing an
8-bit shift register (serial-to-parallel conversion) between
the
P and the controller IC further reduces the I/O lines,
and HCMOS logic provides serial-data entry at 20 MHz
(vs <200 kHz). Such a design could further decrease the
interval required to update the step-motor operation and
reduce the I/O lines on the bus.
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相關代理商/技術參數(shù) |
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