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參數(shù)資料
| 型號(hào)： | PG001 |
| 廠商： | Sanken Electric Co.,Ltd. |
| 英文描述： | Serial Signal Generator IC for SLA7042M and SLA7044M |
| 中文描述： | 串行信號(hào)發(fā)生器集成電路SLA7042M和SLA7044M |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大小： | 179K |
| 代理商： | PG001 |
PG001M
PARALLEL-TO-SERIAL
DATA CONVERTER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Figure 6 — A Latched Input-Bus Configuration
CLOCK
STROBE
SERIAL DATA
SERIAL DATA
Dwg. EK-014-1
1
MODE SELECT
CCW/CW
RESET
VECTOR CONTROL
MODE SELECT2
MONITOR
CLOCKIN
μ
P
P
GND
VDD
+5 V
L
GND
VCC
STROBE
VCC
A
B
At start-up, reseting the counter adds only another
clock interval (per figures 4 and 5). During high-speed
slewing, the
μ
P is only occupied with sending clock
signals and monitoring the readback (MO). Hence, of a
200
μ
s interval, with a slewing rate of 5 kHz, only 5
μ
s is
required to provide the clock input. At slower, more
typical step rates, 5
μ
s becomes an insignificant burden on
the
μ
P controlling the stepping motor.
Other techniques to decrease and unburden the essen-
tial
μ
P I/O lines and control logic are viable. Utilizing an
8-bit shift register (serial-to-parallel conversion) between
the
μ
P and the controller IC further reduces the I/O lines,
and HCMOS logic provides serial-data entry at 20 MHz
(vs <200 kHz). Such a design could further decrease the
interval required to update the step-motor operation and
reduce the I/O lines on the bus.
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