參數(shù)資料
型號: PF5102
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 小信號晶體管
英文描述: N-Channel Switch
中文描述: N-CHANNEL, Si, SMALL SIGNAL, JFET, TO-92
封裝: TO-92, 3 PIN
文件頁數(shù): 1/3頁
文件大小: 26K
代理商: PF5102
2003 Fairchild Semiconductor Corporation
Rev. A, January 2003
P
TO-92
Absolute Maximum Ratings *
T
A
=25
°
C
unless otherwise noted
Symbol
V
DG
Drain-Gate Voltage
V
GS
Gate-Source Voltage
I
GF
Forward Gate Current
T
J
, T
STG
Operating and Storage Junction Temperature Range
* These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1. These ratings are based on a maximum junction temperature of 150 degrees C.
2. These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Electrical Characteristics
T
A
=25
°
C unless otherwise noted
Symbol
Parameter
Off Characteristics
V
(BR)GSS
Gate-Source Breakdwon Voltage
I
GSS
Gate Reverse Current
* Pulse Test: Pulse Width
300
μ
s, Duty Cycle
1.0%
Thermal Characteristics
T
A
=25
°
C unless otherwise noted
Symbol
P
D
Total Device Dissipation
Derate above 25
°
C
R
θ
JC
Thermal Resistance, Junction to Case
R
θ
JA
Thermal Resistance, Junction to Ambient
Parameter
Value
40
-40
50
-55 ~ +150
Units
V
V
A
°
C
Test Condition
Min.
Max.
Units
I
C
= -1.0
μ
A, V
DS
= 0
V
GS
= -15V, V
DS
= 0
V
GS
= -15V, V
DS
= 0, T
A
= 125
°
C
V
DS
= 15V, I
D
= 1.0nA
I
G
= 1.0mA, V
DS
= 0
-40
V
nA
μ
A
V
-1.0
-0.2
-1.6
1.0
V
GS(off)
V
GS(f)
On Characteristics
I
DSS
Small Signal Characteristics
g
fs
Forward Transfer Conductance
g
oss
Output Conductance
C
iss
Input Capacitace
C
rss
Reverse Transfer Capacitance
Gate-Source Cutoff Voltage
Gate-Source Forward Voltage
-0.7
Zero-Gate Voltage Drain Current *
V
DS
= 15V, V
GS
= 0
4.0
20
nA
V
DS
= 15V, V
GS
= 0, f = 1.0KHz
V
DS
= 15V, I
D
= 500
μ
A, f = 1.0KHz
V
DG
= 15V, V
GS
= 0, f = 1.0MHz
V
DG
= 15V, V
GS
= 0, f = 1.0MHz
11,000
μ
mhous
μ
mhous
pF
pF
25
16
6
Parameter
Max.
625
5.0
125
357
Units
mW
mW/
°
C
°
C/W
°
C/W
PF5102
N-Channel Switch
This device is designed for low level analog switching, sample and
hold circuits and chopper stabized amplifiers.
Sourced from process 51.
See J111 for characteristics.
1. Drain 2. Source 3. Gate
1
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