參數(shù)資料
型號(hào): PF48F4P0VBQ0
廠商: Intel Corp.
英文描述: Intel StrataFlash Embedded Memory
中文描述: 英特爾StrataFlash嵌入式存儲(chǔ)器
文件頁數(shù): 41/102頁
文件大小: 1609K
代理商: PF48F4P0VBQ0
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
41
Note:
WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0, Wait asserted low).
7.4
AC Write Specifications
Figure 21.
Synchronous Burst-Mode Four-Word Read Timing
y
A
Q0
Q1
Q2
Q3
R307
R10
R304
R305
R304
R4
R7
R17
R15
R9
R8
R303
R3
R106
R102
R105
R101
R2
R306
R302
R301
CLK [C]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
Table 18.
AC Write Specifications (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Units
Notes
W1
t
PHWL
RST# high recovery to WE# low
150
-
ns
1,2,3
W2
t
ELWL
CE# setup to WE# low
0
-
ns
1,2,3
W3
t
WLWH
WE# write pulse width low
50
-
ns
1,2,4
W4
t
DVWH
Data setup to WE# high
50
-
ns
1,2
W5
t
AVWH
Address setup to WE# high
50
-
ns
W6
t
WHEH
CE# hold from WE# high
0
-
ns
W7
t
WHDX
Data hold from WE# high
0
-
ns
W8
t
WHAX
Address hold from WE# high
0
-
ns
W9
t
WHWL
WE# pulse width high
20
-
ns
1,2,5
W10
t
VPWH
V
PP
setup to WE# high
V
PP
hold from Status read
200
-
ns
1,2,3,7
W11
t
QVVL
0
-
ns
W12
t
QVBL
WP# hold from Status read
0
-
ns
1,2,3,7
W13
t
BHWH
WP# setup to WE# high
200
-
ns
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