- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369995 > PF48F3P0VT00 (Intel Corp.) Intel StrataFlash Embedded Memory PDF資料下載
參數(shù)資料
| 型號： | PF48F3P0VT00 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 英特爾StrataFlash嵌入式存儲器 |
| 文件頁數(shù)： | 67/102頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | PF48F3P0VT00 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當(dāng)前第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
67
12.0
Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an erase command
sequence is issued, and only one block is erased at a time. When a block is erased, all bits within
that block read as logical ones. The following sections describe block erase operations in detail.
12.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of
the block to be erased (see
Section 9.2, “Device Commands” on page 50
). Next, the Block Erase
Confirm command is written to the address of the block to be erased. If the device is placed in
standby (CE# deasserted) during an erase operation, the device completes the erase operation
before entering standby.V
PP
must be above V
PPLK
and the block must be unlocked
(see
Figure 44,
“Block Erase Flowchart” on page 89
).
During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed
events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros only by
programming the block (see
Section 11.0, “Programming Operations” on page 61
).
The Status Register can be examined for block erase progress and errors by reading any address.
The device remains in the Read Status Register state until another command is written. SR[0]
indicates whether the addressed block is erasing. Status Register bit SR[7] is set upon erase
completion.
Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase
operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would
indicate that the WSM could not perform the erase operation because V
PP
was outside of its
acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block,
causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and then cleared
using the Clear Status Register command. Any valid command can follow once the block erase
operation has completed.
12.2
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows
data to be accessed from memory locations other than the one being erased. The Erase Suspend
command can be issued to any device address. A block erase operation can be suspended to
perform a word or buffer program operation, or a read operation within any block except the block
that is erase suspended (see
Figure 41, “Program Suspend/Resume Flowchart” on page 86
).
When a block erase operation is executing, issuing the Erase Suspend command requests the WSM
to suspend the erase algorithm at predetermined points. The device continues to output Status
Register data after the Erase Suspend command is issued. Block erase is suspended when Status
Register bits SR[7,6] are set. Suspend latency is specified in
Section 7.5, “Program and Erase
Characteristics” on page 45
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PF48F4P0VT00 | Intel StrataFlash Embedded Memory |
| PF48F0P0ZB00 | Intel StrataFlash Embedded Memory |
| PF48F2P0ZB00 | Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Capacitance:16.2pF/ft; Conductor Material:Steel; Conductor Plating:Copper RoHS Compliant: Yes |
| PF48F3P0ZB00 | Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Capacitance:16.2pF/ft; Conductor Material:Steel; Conductor Plating:Copper RoHS Compliant: Yes |
| PF48F4P0ZB00 | Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Capacitance:16.2pF/ft; Conductor Material:Steel; Conductor Plating:Copper RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PF48F3P0VTQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F3P0ZB00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F3P0ZBQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F3P0ZT00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F3P0ZTQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。