參數(shù)資料
型號(hào)： PF48F2000P0ZTQ0
廠商： INTEL CORP
元件分類(lèi)： PROM
英文描述： Intel StrataFlash Embedded Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝： 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁(yè)數(shù)： 63/102頁(yè)
文件大?。?/td> 1609K
代理商： PF48F2000P0ZTQ0
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
63
On the next write, a device start address is given along with the first data to be written to the flash
memory array. Subsequent writes provide additional device addresses and data. All data addresses
must lie within the start address plus the word count. Optimum programming performance and
lower power usage are obtained by aligning the starting address at the beginning of a 32-word
boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total
programming time.
After the last data is written to the buffer, the Buffered Programming Confirm command must be
issued to the original block address. The WSM begins to program buffer contents to the flash
memory array. If a command other than the Buffered Programming Confirm command is written to
the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error
occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4]
are set, indicating a programming failure.
When Buffered Programming has completed, additional buffer writes can be initiated by issuing
another Buffered Programming Setup command and repeating the buffered program sequence.
Buffered programming may be performed with V
PP
= V
PPL
or V
PPH
(see
Section 5.2, “Operating
Conditions” on page 30
for limitations when operating the device with V
PP
= V
PPH
).
If an attempt is made to program past an erase-block boundary using the Buffered Program
command, the device aborts the operation. This generates a command sequence error, and Status
Register bits SR[5,4] are set.
If Buffered programming is attempted while V
PP
is below V
PPLK
, Status Register bits SR[4,3] are
set. If any errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
11.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates traditional
programming elements that drive up overhead in device programmer systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see
Figure 43, “BEFP Flowchart”
on page 88
). It uses a write buffer to spread MLC program performance across 32 data words.
Verification occurs in the same phase as programming to accurately program the flash memory cell
to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This enhancement
eliminates three write cycles per buffer: two commands and the word count for each set of 32 data
words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0]
indicates when data from the buffer has been programmed into sequential flash memory array
locations.
Following the buffer-to-flash array programming sequence, the Write State Machine (WSM)
increments internal addressing to automatically select the next 32-word array boundary. This
aspect of BEFP saves host programming equipment the address-bus setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s internal
verification to ensure that the device has programmed properly. This eliminates the external post-
program verification and its associated overhead.
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