- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369995 > PF48F0P0VBQ0 (Intel Corp.) Intel StrataFlash Embedded Memory PDF資料下載
參數(shù)資料
| 型號： | PF48F0P0VBQ0 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 英特爾StrataFlash嵌入式存儲器 |
| 文件頁數(shù)： | 48/102頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | PF48F0P0VBQ0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁當前第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
1-Gbit P30 Family
April 2005
48
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
9.0
Device Operations
This section provides an overview of device operations. The system CPU provides control of all in-
system read, write, and erase operations of the device via the system bus. The on-chip Write State
Machine (WSM) manages all block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash memory
device operations. The CUI does not occupy an addressable memory location; it is the mechanism
through which the flash device is controlled.
9.1
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes upper
address inputs to determine the accessed block. ADV# low opens the internal address latches. OE#
low activates the outputs and gates selected data onto the I/O bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously flows through
if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising
ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be V
IH
; CE# must
be V
IL
).
Bus cycles to/from the P30 device conform to standard microprocessor bus operations.
Table 19
summarizes the bus operations and the logic levels that must be applied to the device control signal
inputs.
9.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted.
CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the
data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus.
See
Section 10.0, “Read Operations” on page 53
for details on the available read modes, and see
Section 14.0, “Special Read States” on page 75
for details regarding the available read states.
Table 19.
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
Notes
Read
Asynchronous
V
IH
V
IH
X
L
L
L
H
Deasserted
Output
Synchronous
Running
L
L
L
H
Driven
Output
Write
V
IH
X
L
L
H
L
High-Z
Input
1
Output Disable
V
IH
V
IH
X
X
L
H
H
High-Z
High-Z
2
Standby
X
X
H
X
X
High-Z
High-Z
2
Reset
V
IL
X
X
X
X
X
High-Z
High-Z
2,3
Notes:
1.
2.
3.
Refer to the
Table 20, “Command Bus Cycles” on page 50
for valid DQ[15:0] during a write operation.
X = Don’t Care (H or L).
RST# must be at V
SS
± 0.2 V to meet the maximum specified power-down current.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PF48F4444PPVBQ0 | Intel StrataFlash Embedded Memory |
| PF48F2P0VBQ0 | Intel StrataFlash Embedded Memory |
| PF48F3P0VBQ0 | Intel StrataFlash Embedded Memory |
| PF48F4P0VBQ0 | Intel StrataFlash Embedded Memory |
| PF48F0P0VB00 | Intel StrataFlash Embedded Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PF48F0P0VT00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F0P0VTQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F0P0ZB00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F0P0ZBQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F0P0ZT00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。