- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367908 > PERICOMPI7C8150 (Pericom Semiconductor Corp.) 2-Port PCI-to-PCI Bridge PDF資料下載
參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 74/106頁 |
| 文件大小： | 904K |
| 代理商： | PERICOMPI7C8150 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁當前第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
64
August 22, 2002 – Revision 1.02
2
Bus Master
Enable
R/W
Controls ability to operate as a bus master on the primary interface
0: do not initiate memory or I/O transactions on the primary
interface and disable response to memory and I/O transactions on
the secondary interface
1: enables 7C8150 to operate as a master on the primary interfaces
for memory and I/O transactions forwarded from the secondary
interface
Reset to 0
No special cycles defined.
Bit is defined as read only and returns 0 when read
Memory write and invalidate not supported.
Bit is implemented as read only and returns 0 when read (unless
forwarding a transaction for another master)
Controls response to VGA compatible palette accesses
3
Special Cycle
Enable
Memory Write
And Invalidate
Enable
R/O
4
R/O
5
VGA Palette
Snoop Enable
R/W
0: ignore VGA palette accesses on the primary
1: enable positive decoding response to VGA palette writes on the
primary interface with I/O address bits AD[9:0] equal to 3C6h,
3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded
and may be any value)
Controls response to parity errors
6
Parity Error
Response
R/W
0: 7C8150 may ignore any parity errors that it detects and continue
normal operation
1: 7C8150 must take its normal action when a parity error is
detected
Reset to 0
Controls the ability to perform address / data stepping
7
Wait Cycle
Control
R/O
0: disable address/data stepping (affects primary and secondary)
1: enable address/data stepping (affects primary and secondary)
Reset to 0
Controls the enable for the P_SERR_L pin
8
P_SERR_L
enable
R/W
0: disable the P_SERR_L driver
1: enable the P_SERR_L driver
Reset to 0
Controls 7C8150’s ability to generate fast back-to-back transactions
to different devices on the primary interface.
9
Fast Back-to-
Back Enable
R/W
0: no fast back-to-back transactions
1: enable fast back-to-back transactions
Reset to 0
Returns 000000 when read
15:10
Reserved
R/O
14.1.4
STATUS REGISTER – OFFSET 04h
Bit
19:16
Function
Reserved
Type
R/O
Description
Reset to 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PESDXL2BT | Low capacitance double bidirectional ESD protection diodes in SOT23 |
| PESDXL2UM | LJT 23C 21#20 2#16 PIN RECP |
| PETAM1270BK300R | BRAID SLEEVING 300M |
| PETAM1270BK50C | 5V RS232 Transceiver with One Receiver Active in SHUTDOWN |
| PETAM1901BK200R | BRAID SLEEVING 300M |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PERINCSPRT5PKM | 制造商:Dialogic Corporation 功能描述:SERVICE;5PK;PERINCIDENT;HW;SUP |
| PER-M18 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Desktop Stand For ONYX-150/ 153/ 154/ 172/ 192/ 1722/ 1922/ 2122/ 2215 (VESA 100) |
| PER-M20 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Desktop Stand For ONYX-170/ 172/ 173/ 174/ 175/ 175S/175X/ 175V/ 190/ 192/ 193/ 195/ 195S/ 195X/195V/ 1722/ 1922/ 2122/ 2217/ 2219 (VESA 100/75) |
| PERMARK-FB-1/2-1.50-9 | 制造商:TE Connectivity 功能描述:PERMARK-FB-1/2-1.50-9 |
| PERMARK-FB-1/2-NO.21-9 | 制造商:TE Connectivity 功能描述:PERMARK-FB-1/2-NO.21-9 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。