參數(shù)資料
型號： PEF2466-H
元件分類： Codec
英文描述： A-Law/u-Law CODEC
中文描述： A-Law/u-Law編解碼器
文件頁數(shù)： 16/73頁
文件大小： 1618K
代理商： PEF2466-H
PEB 2466
PEF 2466
Pin Descriptions
Hardware Reference Manual
7
2001-02-20
21
GNDD
I
Digital Ground
Ground reference for all digital signals.
Internally isolated from GNDA1,2,3,4.
Master Clock Input
1536, 2048, 4096 or 8192 kHz must be applied for any
operation (selected in Register XR5).
MCLK, PCLK, FSC must be synchronous.
Reset Input
Forces the device to default setting mode; active low.
Digital Supply Voltage
+5 V supply for digital circuits (use 100 nF blocking cap.).
Transmit Control Output A
PCM Interface: active if data is transmitted via DXA;
active low, open drain.
Data Transmit to PCM-Highway A
PCM Interface: PCM data for each channel is transmitted
in 8-bit bursts every 125 μs.
Data Receive from PCM-Highway A
PCM Interface: PCM data for each channel is received in
8-bit bursts every 125 μs.
Transmit Control Output B
PCM Interface: active if data is transmitted via DXB;
active low, open drain.
Data Transmit to PCM-highway B
PCM Interface: data for each channel is transmitted in
8-bit bursts every 125 μs.
Data Receive from PCM-highway B
PCM Interface: data for each channel is received in 8-bit
bursts every 125 μs.
Frame Synchronization Clock
8 kHz; reference for individual time slots, indicates start of
PCM frame; MCLK, PCLK, FSC must be synchronous.
PCM Data Clock
128 to 8192 kHz; determines the rate at which PCM data
is shifted into or out of the PCM-ports.
MCLK, PCLK, FSC must be synchronous.
all
22
MCLK
I
all
23
RESET#
I
all
24
V
DDD
I
all
25
TCA#
O
all
26
DXA
O
all
27
DRA
I
all
28
TCB#
O
all
29
DXB
O
all
30
DRB
I
all
31
FSC
I
all
32
PCLK
I
all
Pin
Symbol
Type Function
Ch.
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