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參數(shù)資料
| 型號： | PEEL22CV10AJI-10 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Electrically-Erasable PLD |
| 中文描述： | 電可擦除可編程邏輯器件 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 247K |
| 代理商： | PEEL22CV10AJI-10 |
4 of 10
04-02-009F
PEEL
TM
22CV10A
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
When configuring an I/O macrocell to implement a regis-
tered function (configurations 1 and 2 in Figure 5), the Q
output of the flip-flop drives the feedback term. When con-
figuring an I/O macrocell to implement a combinatorial
function (configurations 3 and 4 in Figure 5), the feedback
signal is taken from the I/O pin. In this case, the pin can be
used as a dedicated input or a bi-directional I/O. (Refer
also to Table 1.)
Additional Macro Cell Configurations
Besides the standard four-configuration macrocell shown in
Figure 5, each PEEL22CV10A provides an additional
eight configurations that can be used to increase design
flexibility. The configurations are the same as provided by
the PEEL18CV8 and PEEL22CV10AZ. However, to
maintain JEDEC file compatibility with standard 22V10
PLDs the additional configurations can only be utilized by
specifying the PEEL22CV10A+ for logic assembly and
programming. To reference these additional configurations
please refer to the PEEL22CV10A+ specifications at the
end of this data sheet.
Design Security
The PEEL22CV10A provides a special EEPROM secu-
rity bit that prevents unauthorized reading or copying of
designs programmed into the device. The security bit is set
by the PLD programmer, either at the conclusion of the pro-
gramming cycle or as a separate step after the device has
been programmed. Once the security bit is set, it is impos-
sible to verify (read) or program the PEEL until the entire
device has first been erased with the bulk-erase function.
Signature Word
The signature word feature allows a 24-bit code to be pro-
grammed
into
the
PEEL22CV10A
PEEL22CV10A+ software option is used. The code can
be read back even after the security bit has been set. The
signature word can be used to identify the pattern pro-
grammed into the device or to record the design revision,
etc.
if
the
Figure 4. Block Diagram of the PEEL 22CV10A I/O Macrocell.
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| PEEL22CV10AJI-7 | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| PEEL22CV10AP-15 | Electrically-Erasable PLD |
| PEEL22CV10AP-25 | Advanced Low Power 5V RS232 Drivers/Receivers with Small Capacitors (Includes LT1130 thru LT1141); Package: SO; No of Pins: 24; Temperature Range: 0°C to +70°C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEEL22CV10AJI-10L | 功能描述:SPLD - 簡單可編程邏輯器件 12 INP 10 I/O 10ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL22CV10AJI12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| PEEL22CV10AJI15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| PEEL22CV10AJI-15 | 功能描述:SPLD - 簡單可編程邏輯器件 U 811-22CV10AJI-15L RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL22CV10AJI-15L | 功能描述:SPLD - 簡單可編程邏輯器件 12 INP 10 I/O 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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