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參數(shù)資料
| 型號(hào)： | PEB2447H |
| 廠商： | SIEMENS AG |
| 英文描述： | Memory Time Switch Extended Large MTSXL |
| 中文描述： | 內(nèi)存定時(shí)開關(guān)擴(kuò)展大型MTSXL |
| 文件頁數(shù)： | 23/51頁 |
| 文件大?。?/td> | 1052K |
| 代理商： | PEB2447H |
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PEB 2447
Operational Description
Semiconductor Group
23
03.97
3
Operational Description
3.1
For a proper initialization of the MTSXL the following procedure is recommended:
First a reset pulse (RES) of at least two CLK clock periods has to be applied. All registers
contain now their reset values. In the next step the connection memories CM0/1 are
initialized by the commands CMDR:STP (1:0) = 01 (CM reset) or CMDR:STP
(2:0) = 011 / 111 (MTSXL selftest).
After having programmed a CM reset command, it takes 4096 clock periods until all
tristate control entries in the CM contain the value “1” (tristated).
If a selftest command was given, it takes 10 240 clock periods to achieve the same
effect. Furthermore the register bit STAR:STOK (selftest o.k.) should read “1” in this
case, in order to prove that there is no fault on the chip. The selftest command must be
given twice: the upper half of data memory (DM0, DM1) is tested when setting
CMDR:STP (2:1) = 01, the lower half of DM0, DM1 is tested by setting CMDR:STP
(2:1) = 11 (see
table 10
).
The activity of the procedures can be monitored in STAR:PACT and an interrupt will
indicate their completion.
In all cases it is important, that the outputs are tristated by MODR:PSB = 0.
Initialization Procedure
3.2
The operation mode of the device is fixed by programming MODR:MD (1:0) (see
table 9
).
Operation Mode
3.3
The connection memories and data memories are accessible through the indirect access
registers MACH, MAAL, MRDH, MRDL, MWDH and MWDL. An indirect access is
actually started by writing register MACH (Memory Access Address/Code Register
High). The code value inherent in this register defines, what action has to be performed.
The low byte of the complete access address must be programmed to MAAL (Memory
Access Address Register Low) before writing to MACH. If data are necessary to perform
the access (e.g. in write operations), they have to be entered into MWDH (Memory Write
Data Register High) and MWDL (Memory Write Data Register Low) before. In read
accesses the corresponding registers MRDH (Memory Read Data Register High) and
MRDL (Memory Read Data Register Low) contain the required information after the
internal read process is completed.
Indirect Access Registers
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