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參數(shù)資料
| 型號(hào)： | PEB2445 |
| 廠商： | SIEMENS AG |
| 英文描述： | Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| 中文描述： | 多點(diǎn)交換和會(huì)議組-衰減MUSAC -阿 |
| 文件頁(yè)數(shù)： | 29/70頁(yè) |
| 文件大?。?/td> | 1236K |
| 代理商： | PEB2445 |
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PEB 2445
Functional Description
Semiconductor Group
29
02.96
The four most significant bits of the clock shift register are of interest for the input lines.
They only affect the odd input lines (see
chapter 4.6.2
): The frame structure can be
advanced by the number of bit periods programmed to the RS2, RS1 and RS0 bits of the
CSR
. For example, programming the
CSR
with (1100XXXX) a new frame starts 6-bit
periods before the rising edge of the SP pulse.
Selecting RRE to logical 1 the frame is delayed by half a bit period (see
figure 12
). The
data is then sampled in the middle of the respective bit period for all data rates.
The last line of
figure 12
shows the sampling instants for the
CSR
entry (1001XXXX).
Then the input frame is advanced by 4-bit periods and delayed by a half resulting in an
3 1/2-clock period advancement of the input frame. For further examples refer to
figure 20
.
Thus the frame structure may be selected to begin at any 1/2-bit period value between
an resulting advancement of 7-bit periods and a resulting delay of 1/2 a bit period.
Setting
CSR
= 0X
H
the same timing conditions apply to even and odd inputs. Then all
system interface inputs are processed in the same way they are in the standard
configuration.
Output Buffer
The output buffer rearranges the data read from the speech memory. It basically
converts the parallel data to serial data. Depending on the validity bit the output buffer
outputs the data or switches the line to high impedance. The most significant bits of the
256 words in the connection memory are interpreted as validity bits for the 256 possible
output channels: A logical 0 enables the programmed connection, a logical 1 tristates the
output.
The mode register (
MOD
) bits Ml1, Ml0, MO1 and MO0 control this process. The
possible output modes are listed in
table 3
.
Table 3
Possible Output Modes
Output Modes
8
4
2
1
×
8192
2
×
4096
Type
Single mode
Single mode
Single mode
Mixed mode
Mixed mode
×
×
×
+
+
2048
4096
8192
4
×
2048
4
×
2048
kbit/s
kbit/s
kbit/s
kbit/s
kbit/s
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PEB2445-N | Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| PEB2445N | LTM4600 Evaluation Kit |
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| PEB2447H | Memory Time Switch Extended Large MTSXL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEB2445N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:?Multipoint Switching and Conferencing Unit - Attenuation? |
| PEB2445-N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| PEB2445P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM， Other/Special/Miscellaneous |
| PEB2447 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447H | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
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