參數(shù)資料
型號： PEB2245N
廠商： SIEMENS AG
英文描述： ?Multipoint Switching and Conferencing Unit - Attenuation?
中文描述： ？多點(diǎn)交換和會議股-衰減？
文件頁數(shù)： 31/70頁
文件大?。?/td> 1021K
代理商： PEB2245N
PEB 2245
Semiconductor Group
31
Indirect access to the CFR, CSR, CM or CCM:
An indirect access is performed by reading/writing three consecutive bytes (first byte = control byte,
second byte = data byte, third byte = address byte) to/from IAR.
The bits K2 … K0 determine whether the CFR, the CSR, the CM or the CCM shall be accessed,
whether a write or read operation shall be performed and whether the first or the second memory
access shall be executed. (To describe a conference two accesses to the CCM are necessary). The
bits D7 … D0 contain the information which shall be written into the control memories or the indirect
registers. The address byte indicates which one of the indirect registers shall be accessed or in
which memory location the data shall be written. An exact definition is given in
chapter Indirect
Access Register
.
Before an indirect access is started, the Z- and B bits of the status register must be 0. With the first
instruction the Z-bit is set (
see chapter Status Register
). After the third instruction the MUSAC
accesses the memory location. This access requires maximally 900 ns. After the access is finished
the Z bit is reset.
Figure 16 a)
illustrates a write operation on the IAR.
It is possible to read or write the direct access registers while an indirect access is in progress. Thus
a register may be read in the time intervals that separate the three sequential indirect access
instructions. Also, the current indirect access may be aborted by setting the MOD:RI. One indirect
register access has to be completed before the next one can be started.
To read the indirect registers or the CM two sequences of three instructions each have to be
programmed. In the first sequence the MUSAC is instructed which register of CM address to read.
The data transferred to the PEB 2245 in this first sequence is of no significance. With the first write
instruction STA:Z is set. After the first 3 instructions the MUSAC needs 900 ns to write the result to
the IAR. The status register bit Z is reset after maximally 900 ns. Then 3 read operations follow.
Again, STA:Z is set with the first read instruction. The 3 instructions read 3 bytes from the IAR.
Figure 16 b)
shows this procedure. After the third read operation the PEB 2245 needs another
900 ns to reset the indirect access mechanism and the Z bit in the status register. In CCM read
accesses three sequences of three instructions (two write sequences and one read sequence;
see
figure 16 c)
) are necessary.
Bit 7
Bit 0
K2
K1
K0
0
0
DI0
D9
D8
Control Byte
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
IA7
IA6
IA5
IA4
IA3
IA2
IA1
IA0
Address Byte
相關(guān)PDF資料
PDF描述
PEB22522FV21 MULTI BIT RATE INTEGRATED CIRCUIT
PEB22522 MULTI BIT RATE INTEGRATED CIRCUIT
PEB22522F ?Multi Bit-rate Integrated Circuit (MuBIC-2)?
PEB2254 ICs for Communications
PEB2254-H ICs for Communications
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PEB2245-N 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:multipoint switching and conferencing unit (musac)
PEB22504 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Quad Line Interface Unit for E1⁄T1⁄J1 QuadLIU
PEB22504HT-V11 功能描述:IC INTERFACE QUAD 100-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:* 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
PEB22522 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MULTI BIT RATE INTEGRATED CIRCUIT
PEB22522F 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:?Multi Bit-rate Integrated Circuit (MuBIC-2)?
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*