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參數(shù)資料
| 型號(hào)： | PE97632ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| 中文描述： | 3.2 GHz的Δ-Σ調(diào)制的低相位噪聲應(yīng)用分?jǐn)?shù)N頻率合成器 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 373K |
| 代理商： | PE97632ES |
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Advance Information
PE97632
Page 4 of 16
2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0205-02
│
UltraCMOS RFIC Solutions
Pin No.
Pin
Name
Valid
Mode
Type
Description
47
F
in
Both
Input
Prescaler input from the VCO. 3.2 GHz max frequency.
48
F
in
Both
Input
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50
Ω
resistor directly to the ground plane.
49
GND
Downbond
Ground
Logical “NAND” of PD_
U
and PD_
D
terminated through an on chip, 2 k
Ω
series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
50
CEXT
Both
Output
51
LD
Both
Output
52
D
OUT
Both
Output
Data out function, enabled in enhancement mode.
53
V
DD
(Note 1)
Output driver/V
DD
.
54
GND
Downbond
Ground
55
PD_
D
Both
Output
PD_
D
pulses down when f
p
leads f
c
. PD_
U
is driven to GND when CPSEL = “High”.
56
NC
Both
No Connect
57
PD_
U
Both
Output
PD_
U
pulses down when f
c
leads f
p
. PD_
D
is driven to GND when CPSEL = “High”.
58
GND
Downbond
Ground
59
V
DD
(Note 1)
Output driver/V
DD
.
60
V
DD
(Note 1)
Phase detector V
DD
.
61
GND
Downbond
Ground
62
f
r
Both
Input
Reference frequency input.
63
V
DD
(Note 1)
Reference V
DD
.
64
V
DD
(Note 1)
Digital core V
DD
.
GND
Downbond
Ground
65
ENH
Both
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
66
NC
Both
No Connect
67
MS2_SEL
Both
Input
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
68
RND_SEL
Both
Input
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 2
19
.
Note 1: All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
Note 2:
All digital input pins have 70 k
pull-down resistors to ground.
46
V
DD
(Note 1)
Prescaler V
DD
.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PE9763EK | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| PE9763ES | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| PE9764 | 制造商:PASTERNACK 制造商全稱:Pasternack Enterprises, Inc. 功能描述:Precision 1.85mm Female to SSMA Male Adapter |
| PE9765 | 制造商:PASTERNACK 制造商全稱:Pasternack Enterprises, Inc. 功能描述:Precision 1.85mm Female to SSMA Female Adapter |
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