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參數(shù)資料
| 型號(hào)： | PE4302-52 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 50 OHM RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
| 中文描述： | 50歐姆射頻數(shù)字衰減器6位，31.5分貝，直流4.0千兆赫 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 456K |
| 代理商： | PE4302-52 |
Product Specification
PE4302
Page 8 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0056~02D
│
UltraCMOS RFIC Solutions
Table 7. 6-Bit Attenuator Serial Programming
Register Map
Table 9. Parallel Interface AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Figure 18. Parallel Interface Timing Diagram
Table 8. Serial Interface AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Figure 17. Serial Interface Timing Diagram
LE
Clock
Data
MSB
LSB
t
LESUP
t
SDSUP
t
SDHLD
t
LEPW
B5
C16
↑
B4
C8
B3
C4
B2
C2
B1
C1
B0
C0.5
↑
LSB (last in)
MSB (first in)
t
PDSUP
t
PDHLD
Parallel Data
C16:C0.5
LE
t
LEPW
Symbol
Parameter
Min
Max
Unit
f
Clk
Serial data clock fre-
quency (Note 1)
Serial clock HIGH time
Serial clock LOW time
LE set-up time after last
clock falling edge
LE minimum pulse width
Serial data set-up time
before clock rising edge
Serial data hold time
after clock falling edge
10
MHz
t
ClkH
t
ClkL
30
30
10
ns
ns
ns
t
LESUP
t
LEPW
30
10
ns
ns
t
SDSUP
t
SDHLD
10
ns
Note: f
is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked at
10 MHz to verify fclk specification.
Symbol
Parameter
Min
Max
Unit
t
LEPW
LE minimum pulse width
10
ns
t
PDSUP
Data set-up time before
rising edge of LE
Data hold time after
falling edge of LE
10
ns
t
PDHLD
10
ns
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| PE4302DS | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:50 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
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| PE4304 | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:75 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC - 2.0 GHz |
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| PE4305 | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:50 Ω RF Digital Attenuator 5-bit, 15.5 dB, DC - 4.0 GHz |
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