參數(shù)資料
型號(hào)： PE-65966
廠商： Exar Corporation
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： E3/DS3/STS-1線路接口單元
文件頁(yè)數(shù)： 40/55頁(yè)
文件大?。?/td> 608K
代理商： PE-65966
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
á
36
4.0
The XRT7300 supports equipment diagnostic activi-
ties by supporting the following Loop-Back modes in
the chip:
Analog Local Loop-Back
Digital Local Loop-Back
Remote Loop-Back.
4.1
T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
When the XRT7300 is configured to operate in the
Analog Local Loop-Back Mode, the XRT7300 ignores
any signals that are input to the RTIP and RRING in-
put pins. The Transmitting Terminal Equipment trans-
mits clock and data into the XRT7300 via the TPDA-
TA, TNDATA and TCLK input pins. This data is pro-
cessed through the Transmit Clock Duty Cycle Adjust
DIAGNOSTIC FEATURES OF THE XRT7300
PLL and the HDB3/B3ZS Encoder. Finally, this data
outputs to the line via the TTIP and TRING output
pins and is looped back into the AGC/Receive Equal-
izer Block. Consequently, this data is also processed
through the Receive Section of the XRT7300. After
this post-loop-back data has been processed through
the Receive Section it outputs to the Near-End Re-
ceiving Terminal Equipment via the RPOS, RNEG,
RCLK1 and RCLK2 output pins.
Figure 28 illustrates the path that the data takes when
the chip is configured to operate in the Analog Local
Loop-Back Mode.
The XRT7300 can be configured to operate in the An-
alog Local Loop-Back Mode by employing either one
of the following two steps:
F
IGURE
26. T
HE
T
YPICAL
I
NTERFACE
FOR
THE
T
RANSMISSION
OF
D
ATA
IN
A
S
INGLE
-R
AIL
F
ORMAT
F
ROM
THE
R
ECEIVE
S
ECTION
OF
THE
XRT7300
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
Exar E3/DS3/STS-1 LIU
Receive
Logic
Block
RxPOS
RCLK1, 2
RPOS
RCLK1, 2
F
IGURE
27. T
HE
B
EHAVIOR
OF
THE
RPOS
AND
RCLK1 O
UTPUT
S
IGNALS
W
HILE
THE
XRT7300
IS
T
RANSMITTING
S
INGLE
-R
AIL
D
ATA
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
RCLK1
RPOS
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