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參數(shù)資料
| 型號： | PDU17F-4M |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 70K |
| 代理商： | PDU17F-4M |
PDU17F
Doc #97005
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
7-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU17F)
FEATURES
PACKAGES
Digitally programmable in 128 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
10 T
2
L fan-out capability
Fits standard 40-pin DIP socket
Auto-insertable
FUNCTIONAL DESCRIPTION
The PDU17F-series device is a 7-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A6-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
Programmed delay tolerance:
5% or 2ns,
whichever is greater
Inherent delay (TD
0
):
13ns typical (OUT)
12ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (T
AIS
):
Disable to output delay (T
DISO
):
6ns typ. (OUT)
Operating temperature:
0
°
to 70
°
C
Temperature coefficient:
100PPM/
°
C (excludes TD
0
)
Supply voltage V
CC
:
5VDC
±
5%
Supply current:
I
CCH
= 68ma
I
CCL
= 86ma
Minimum pulse width:
8% of total delay
10ns
1997 Data Delay Devices
data
delay
devices,
inc.
3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N/C
OUT/
OUT
EN/
GND
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
GND
N/C
EN/
N/C
IN
N/C
GND
VCC
N/C
A0
A1
A2
VCC
N/C
A3
A4
A5
VCC
N/C
N/C
N/C
N/C
VCC
N/C
A6
N/C
N/C
PDU17F-xx
DIP
PDU17F-xxC5
Gull-Wing
PDU17F-xxM
Military DIP
PDU17F-xxMC5
Military Gull-Wing
PIN DESCRIPTIONS
IN
OUT
OUT/ Inverted Output
A0-A6 Address Bits
EN/
Output Enable
VCC
+5 Volts
GND
Ground
Delay Line Input
Non-inverted Output
DASH NUMBER SPECIFICATIONS
Part
Number
PDU17F-.5
PDU17F-1
PDU17F-2
PDU17F-3
PDU17F-4
PDU17F-5
PDU17F-6
PDU17F-8
PDU17F-10
Incremental Delay
Per Step (ns)
.5
±
.3
1
±
.5
2
±
.5
3
±
1.0
4
±
1.0
5
±
1.5
6
±
1.5
8
±
2.0
10
±
2.0
Total Delay
Change (ns)
63.5
±
3.2
127
±
6.4
254
±
12.7
381
±
19.1
508
±
25.4
635
±
31.8
762
±
38.1
1,016
±
50.8
1,270
±
63.5
NOTE: Any dash number between .5 and 10 not
shown is also available.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PDU-17F-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| PDU-17F-9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| PDU18F-10 | 制造商:IC'S/TRANSISTORS/DIO 功能描述: |
| PDU-18F-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| PDU-18F-9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
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