- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369986 > PDU1032H-2C4 Delay Line PDF資料下載
參數(shù)資料
| 型號(hào)： | PDU1032H-2C4 |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁(yè)數(shù)： | 5/5頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | PDU1032H-2C4 |
PDU1016H
Doc #97044
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
-5.0V
±
0.1V
Input Pulse:
OUTPUT:
Load:
C
load
:
Threshold:
50
to -2V
5pf
±
10%
(V
OH
+ V
OL
) / 2
(Rising & Falling)
Standard 10KH ECL
levels
50
Max.
2.0 ns Max. (measured
between 20% and 80%)
PW
IN
= 1.5 x Total Delay
PER
IN
= 10 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
OUT
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
PULSE
GENERATOR
IN
ADDRESS SELECT
Timing Diagram For Testing
T
RISE
T
FALL
PER
IN
PW
IN
T
RISE
T
FALL
20%
20%
80%
50%
50%
50%
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDU1032H-2M | Delay Line |
| PDU1032H-2MC4 | Delay Line |
| PDU1032H-3 | Programmable Delay Line |
| PDU1032H-3C4 | Delay Line |
| PDU1032H-3M | Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDU1032H-2C5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H) |
| PDU1032H-2M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H) |
| PDU1032H-2MC4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| PDU1032H-2MC5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H) |
| PDU1032H-3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。