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參數(shù)資料
| 型號(hào)： | PDU10256H-.5MC5 |
| 廠商： | Data Delay Devices, Inc. |
| 英文描述： | 8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
| 中文描述： | 8位，經(jīng)過ECL接口可編程延遲線（系列PDU10256H） |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 45K |
| 代理商： | PDU10256H-.5MC5 |
PDU10256H
Doc #97047
12/17/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
8-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU10256H)
FEATURES
PACKAGES
Digitally programmable in 128 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits 48-pin DIP socket
PIN DESCRIPTIONS
IN
OUT
A0-A7 Address Bits
ENB
Output Enable
VEE
-5 Volts
GND
Ground
Signal Input
Signal Output
FUNCTIONAL DESCRIPTION
The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TD
A
, from the
input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following
formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device, and TD
0
is the inherent delay of
the device. The incremental delay is specified by the dash number of the device and can range from
0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this
signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain
asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance:
5% or 2ns,
whichever is greater
Inherent delay (TD
0
):
12ns typical
Setup time and propagation delay:
Address to input setup (T
AIS
):
Disable to output delay (T
DISO
):
1.7ns typical
Operating temperature:
0
°
to 70
°
C
Temperature coefficient:
100PPM/
°
C (excludes TD
0
)
Supply voltage V
EE
:
-5VDC
±
5%
Power Dissipation:
925mw typical (no load)
Minimum pulse width:
16% of total delay
3.6ns
1997 Data Delay Devices
data
delay
devices,
inc.
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
ENB
IN
N/C
N/C
A2
A1
VEE
A0
N/C
A5
A4
VEE
A3
N/C
N/C
N/C
N/C
N/C
N/C
A7
VEE
A6
GND
IN
A6
VEE
GND
ENB
A0
VEE
48
47
42
41
1
2
7
8
GND
OUT
A1
A2
GND
A3
VEE
40
34
33
9
15
16
GND
A4
A5
32
25
17
19
23
24
GND
A7
PDU10256H-xxC5
PDU10256H-xxMC5 Mil SMD
SMD
PDU10256H-xx
PDU10256H-xxM Mil DIP
DIP
DASH NUMBER SPECIFICATIONS
Part
Number
PDU10256H-.5
PDU10256H-1
PDU10256H-2
PDU10256H-3
PDU10256H-4
PDU10256H-5
PDU10256H-6
PDU10256H-8
PDU10256H-10
Incremental Delay
Per Step (ns)
0.5
±
0.3
1.0
±
0.5
2.0
±
0.5
3.0
±
1.0
4.0
±
1.0
5.0
±
1.5
6.0
±
1.5
8.0
±
2.0
10.0
±
2.0
Total
Delay (ns)
127.5
±
6.4
255
±
12.8
510
±
25.5
765
±
38.2
1020
±
51.0
1275
±
63.8
1530
±
76.5
2040
±
102
2550
±
128
NOTE: Any dash number between .5 and 10
not shown is also available.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDU10256H-1 | 8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
| PDU10256H-10 | 8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
| PDU10256H-10C5 | 8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
| PDU10256H-10M | 8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
| PDU10256H-10MC5 | 8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDU-10256H-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| PDU10256H-6 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
| PDU10256H-6C5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
| PDU10256H-6M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
| PDU10256H-6MC5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) |
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