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參數(shù)資料
| 型號： | PDSP16510AGCPR |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Stand Alone FFT Processor |
| 中文描述： | 攻殼機(jī)動隊(duì)FFT處理器 |
| 文件頁數(shù)： | 21/23頁 |
| 文件大?。?/td> | 190K |
| 代理商： | PDSP16510AGCPR |
PDSP16510A
21
ABSOLUTE MAXIMUM RATINGS [See Notes]
Supply voltage Vcc
Input voltage V
Output voltage V
Clamp diode current per pin I
(see note 2)
Static discharge voltage (HMB)
Storage temperature T
Junction Temperature, Commercial
Junction temperature, Industrial
Junction Temperature, Military
Package power dissipation
-0.5V to 7.0V
-0.5V to Vcc + 0.5V
-0.5V to Vcc + 0.5V
18mA
500V
-65
°
C to 150
°
C
100
°
C
115
°
C
155
°
C
5000mW
Delay from output
high to output
high impedance
Test
Waveform - measurement level
Delay from output
low to output
high impedance
H
V
0.5V
V
0.5V
L
1.5V
0.5V
1.5V
0.5V
Delay from output
high impedance to
output low
Delay from output
high impedance to
output high
V - Voltage reached when output driven hig
V - Voltage reached when output driven low
Units
V
V
V
V
μ
A
pF
μ
A
mA
Symbol
V
OH
V
OL
V
IH
V
IL
I
IN
C
IN
I
OZ
I
SC
Min.
2.4
-
2.0
-
-10
-50
10
Characteristic
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output S/C current
Max.
-
0.4
-
0.8
+10
+50
300
Value
Typ.
10
NOTES ON MAXIMUM RATINGS
1. Exceeding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.
2. Maximum dissipation or 1 second should not be exceeded,
only one output to be tested at any one time.
3. Exposure to absolute maximum ratings for extended
periods may affect device reliablity.
4. Current is defined as positive into the device.
ELECTRICAL CHARACTERISTICS
Operating Conditions (unless otherwise state)
PDSP16510A C0Tamb = 0 C to + 70
°
C.
PDSP16510A B0 Tamb = -40 C to + 85
°
C.
PDSP16510A A0 Tamb = -55 C to +125
°
C. Vcc = 5.0v
±
10%
Vcc = 5.0v
±
5%
Vcc = 5.0v
±
10%
Characteristic Symbol Min Max
Clock Frequency ( MHz )
DC 40
Clock High Period ( ns ) T
CH
13
Clock Low Period ( ns ) T
CL
10
Max DOS, DIS Frequency
D
F
Conditions
Max
high time is 1msec
Less than 1024 points or Mult Dev Mode 1
Note F = 4
6 + 0.001
T
CL
Max DIS Frequency
D
Max DOS Frequency
D
1024 points or Mult Dev Modes 2 and 3
Notes
I
OH
= 4mA
I
= -4mA
SCLK, DIS, DOS, DEN need 3V
DEN needs 0.7V max
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
V
CC
= Max
SWITCHING CHARACTERISTICS
SCLK to DIS/DOS RELATIONSHIP
Both DIS and DOS must be synchronous to SCLK. Ideally they should both be produced from SCLK, in which case the
SCLK rising edge would either be first or coincident with the DIS and DOS rising edges.
In any event, the rising edge of SCLK must not fall between 2ns and 10ns after the rising edge of either DIS or DOS
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