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參數(shù)資料
| 型號(hào)： | PDSP16116DB0GG |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 16 X 16 Bit Complex Multiplier |
| 中文描述： | 16 × 16位乘法器復(fù)雜 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 270K |
| 代理商： | PDSP16116DB0GG |
PDSP16116
12
CLK
INPUT DATA X AND Y
OUTPUT P PORTS
OUTPUT SFTA1:0
VALID DATA
INPUT CONTROLS CEX AND CEY
t
CP
t
DS
t
DH
t
CLK
t
CLKH
t
CLKL
t
CSFTA
t
CSFTA
VALID DATA
t
CONS
t
CES
t
CEH
t
CONH
t
WS
t
WH
INPUT CONTROLS CONX AND CONY
INPUT CONTROL WTB1:0
Fig. 9 Normal mode timing
OER AND OEI
OUTPUT P PORTS
HIGH Z
t
OPLZ
t
OPZL
HIGH Z
t
OPZH
t
OPHZ
HIGH Z
Fig. 10 Output tristate timing
V
H
0·5V
Delay from
output high
to output
high Z (t
OPHZ
)
0·5V
0·5V
0·5V
V
L
1·5V
1·5V
Delay from
output low
to output
high Z (t
OPLZ
)
Delay from
output high Z
to output low
(t
OPZL
)
Delay from
output high Z
to output high
(t
OPZH
)
Test
Waveform measurement level
V
is the voltage reached when the output is driven high
VL is the voltage reached when the output is driven low
V
T
= 0V
V
T
= V
DD
Three state delay measurement load
V
T
DUT
30p
1·5k
Fig. 11 Three state delay measurement
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDSP16116MCGGDR | 16 X 16 Bit Complex Multiplier |
| PDSP16116A | 16 By 16 Bit Complex Multiplier(16×16位 復(fù)雜乘法器) |
| PDSP16116MC | 16 By 16 Bit Complex Multiplier(16×16位 復(fù)雜乘法器) |
| PDSP16116 | 16 By 16 Bit Complex Multiplier(16×16位 復(fù)雜乘法器) |
| PDSP16256C0 | Programmable FIR Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16116MC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:16 by 16 Bit Complex Multiplier |
| PDSP16116MCAC1R | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:16 by 16 Bit Complex Multiplier |
| PDSP16116MCGC1R | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:16 by 16 Bit Complex Multiplier |
| PDSP16116MCGGDR | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier |
| PDSP16256 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter |
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