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參數(shù)資料
| 型號(hào)： | PDM41256LA12TSOI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256K Static RAM 32K x 8-Bit |
| 中文描述： | 256K靜態(tài)RAM 32K的× 8位 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 73K |
| 代理商： | PDM41256LA12TSOI |
PDM41256
Rev. 2.0 - 7/17/96
3-39
1
2
3
4
5
6
7
8
9
10
11
12
Low V
CC
Data Retention Waveform
Data Retention Electrical Characteristics (LA Version Only)
NOTES: (For three previous Electrical Characteristics tables)
1. The device is continuously selected. Chip Enable is held in its active state.
2. The address is valid prior to or coincident with the latest occuring Chip Enable.
3. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
.
4. This parameter is sampled.
5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage
6. Vcc = 5V ± 5%.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DR
V
CC
for Retention Data
2
—
—
V
I
CCDR
Data Retention Current
CE
≥
V
CC
– 0.2V
V
IN
≥
V
CC
– 0.2V
or
≤
0.2V
V
CC
= 2V
—
95
500
μA
V
CC
= 3V
—
350
750
μA
t
CDR
t
R(4)
Chip Deselect to Data Retention Time
0
—
—
ns
Operation Recovery Time
t
RC
—
—
ns
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