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參數(shù)資料
| 型號： | PDI1394P25 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 1-port 400 Mbps physical layer interface |
| 中文描述： | 1端口400 Mbps的物理層接口 |
| 文件頁數(shù)： | 35/42頁 |
| 文件大小： | 233K |
| 代理商： | PDI1394P25 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
35
The sequence of events for resetting the PHY-LLC interface when it
is in the nondifferentiated mode of operation (ISO terminal is high) is
as follows:
1. Normal operation. Interface is operating normally, with LPS
asserted, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line. In the above diagram, the LPS signal is shown
as a non-pulsed level signal. However, it is permissible to use a
pulsed signal for LPS in a direct connection between the PHY
and LLC; a pulsed signal is required when using an isolation
barrier (whether of the Philips Bus Holder type or Annex J type).
2. LPS deasserted. The LLC deasserts the LPS signal and, within
1.0 ms, terminates any request or interface bus activity, places
its CTL and D outputs into a high-impedance state, and drives
its LREQ output low.
3. Interface reset. After T
LPS_RESET
time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and drives
its CTL and D outputs low. The PHY-LLC interface is now in the
reset state.
4. Interface restored. After the minimum T
RESTORE
time, the LLC
may again assert LPS active. (The minimum T
RESTORE
interval
provides sufficient time for the biasing networks used in Annex J
type isolation barrier circuits to stabilize and reach a quiescent
state if the isolation barrier has somehow become unbalanced.)
When LPS is asserted, the interface will be initialized as
described below.
If the LLC continues to keep the LPS signal deasserted, it requests
that the interface be disabled. The PHY disables the interface when
it observes that LPS has been deasserted for T
LPS_DISABLE
. When
the interface is disabled, the PHY sets its CTL and D outputs as
stated above for interface reset, but also stops SYSCLK activity. The
interface is also placed into the disabled condition upon a hardware
reset of the PHY. The timing for interface disable is shown in
Figure 22 and Figure 23.
When the interface is disabled, the PHY will enter a low-power state
if none of its ports is active.
T
LPS_RESET
T
LPS_DISABLE
ISO
SYSCLK
CTL0, CTL1
D0 – D7
LREQ
LPS
(low)
(a)
(c)
(b)
T
LPSL
T
LPSH
SV01812
(d)
Figure 22.
Interface Disable, ISO Low
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394P25BD | 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| PDI1394P25BD,118 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Tape and Reel |
| PDI1394P25BD,151 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays |
| PDI1394P25BD,157 | 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| PDI1394P25BD-S | 功能描述:IC IEEE 1394 LINK CTRLR 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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