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參數資料
| 型號： | PDI1394L11BA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1394 AV link layer controller |
| 中文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數： | 29/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394L11BA |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
29
subsequently interrupts the status transfer. Register contents are
considered to have been successfully transmitted only when all
8 bits of the register have been sent. A status transfer is retried after
being interrupted only if any status flags remain to be sent, or if a
register transfer has not yet completed.
The definition of the bits in the status transfer is shown in Table 18,
and the timing is shown in Figure 15.
The sequence of events for a status transfer is as follows:
Status transfer initiated. the PHY indicates a status transfer by
asserting status on the CTL lines along with the status data on the
D0 and D1 lines (only 2 bits of status are transferred per cycle).
Normally (unless interrupted by a receive operation), a status
transfer will be either 2 or 8 cycles long. A 2-cycle (4 bit) transfer
occurs when only status information is to be sent. An 8-cycle
(16 bit) transfer occurs when register data is to be sent in addition
to any status information.
Status transfer terminated. The PHY normally terminates a status
transfer by asserting idle on the CTL lines. If a bus reset is
pending, the PHY may also assert Grant on the CTL line
immediately following a complete status transfer.
Table 18. Status Bits
BIT(S)
NAME
DESCRIPTION
0
Arbitration Reset Gap
Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as
defined in the IEEE 1394–1995 standard). This bit is used by the LLC in the busy/retry state machine.
Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the
IEEE 1394–1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.
Indicates that the PHY has entered the bus reset state.
1
Subaction gap
2
Bus reset
3
Interrupt
Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a
cable-power voltage falling too low, a state time-out, or a port status change.
This field holds the address of the PHY register whose contents are being transferred to the LLC.
4–7
Address
8–15
Data
This field holds the register contents.
SYSCLK
(a)
(b)
CTL0, CTL1
D0, D1
00
00
00
01
00
01
S[14:15]
S[0:1]
SV01759
Figure 15.
Status Transfer Timing
18.3
Whenever the PHY detects the data-prefix state on the serial bus, it
initiates a receive operation by asserting Receive on the CTL terminals
and a logic 1 on each of the D terminals (“data-on” indication). The
PHY indicates the start of a packet by placing the speed code
(encoded as shown in Table 19) on the D terminals, followed by
packet data. The PHY holds the CTL terminals in the Receive state
until the last symbol of the packet has been transferred. The PHY
indicates the end of packet data by asserting Idle on the CTL
terminals. All received packets are transferred to the LLC. Note that
the speed code is part of the PHY-LLC protocol and is not included in
the calculation of CRC or any other data protection mechanisms.
Receive
Table 19. Speed Code for the Receiver
D0–D7
DATA RATE
0000 0000
S100
0100 0000
S200
0101 0000
S400
1111 1111
“data-on” indication
It is possible for the PHY to receive a null packet, which consists of
the data-prefix state on the serial bus followed by the data-end state,
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相關代理商/技術參數 |
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| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller |
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