
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U16228EJ2V0UD
164
Figure 6-18. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 0n (TMC0n)
7
0
6
0
5
0
4
0
TMC0n3
1
TMC0n2
1
TMC0n1
0
OVF0n
0
TMC0n
Clears and starts on match between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
7
0
6
0
5
0
4
0
3
0
CRC0n2
0
CRC0n1
×
CRC0n0
0
CRC0n
CR00n used as compare register
CR01n used as compare register
(c) 16-bit timer output control register 0n (TOC0n)
7
0
OSPT0n
0
OSPE0n
0
TOC0n4
1
LVS0n
0/1
LVR0n
0/1
TOC0n1
1
TOE0n
1
TOC0n
Enables TO0n output.
Inverts output on match between TM0n and CR00n.
Specifies initial value of TO0n output F/F (setting “11” is prohibited).
Inverts output on match between TM0n and CR01n.
Disables one-shot pulse output.
(d) Prescaler mode register 0n (PRM0n)
ES1n1
0/1
ES1n0
0/1
ES0n1
0/1
ES0n0
0/1
3
0
2
0
PRM0n1
0/1
PRM0n0
0/1
PRM0n
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Cautions 1. Values in the following range should be set in CR00n and CR01n:
0000H
≤
CR01n < CR00n
≤
FFFFH
2. The cycle of the pulse generated through PPG output (CR00n setting value + 1) has a duty of
(CR01n setting value + 1)/(CR00n setting value + 1).
Remark
×
: Don’t care
n = 0:
n = 0, 1:
μ
PD780133, 780134, 78F0134, 780136, 780138, 78F0138
μ
PD780131, 780132