
CHAPTER 28 INSTRUCTION SET
User’s Manual U16228EJ2V0UD
463
Clocks
Flag
Instruction
Group
Mnemonic
Operands
Bytes
Note 1
Note 2
Operation
Z AC CY
CALL
!addr16
3
7
(SP
1)
←
(PC + 3)
H
, (SP
2)
←
(PC + 3)
L
,
PC
←
addr16, SP
←
SP
2
CALLF
!addr11
2
5
(SP
1)
←
(PC + 2)
H
, (SP
2)
←
(PC + 2)
L
,
PC
15
11
←
00001, PC
10
0
←
addr11,
SP
←
SP
2
CALLT
[addr5]
1
6
(SP
1)
←
(PC + 1)
H
, (SP
2)
←
(PC + 1)
L
,
PC
H
←
(00000000, addr5 + 1),
PC
L
←
(00000000, addr5),
SP
←
SP
2
BRK
1
6
(SP
1)
←
PSW, (SP
2)
←
(PC + 1)
H
,
(SP
3)
←
(PC + 1)
L
, PC
H
←
(003FH),
PC
L
←
(003EH), SP
←
SP
3, IE
←
0
RET
1
6
PC
H
←
(SP + 1), PC
L
←
(SP),
SP
←
SP + 2
RETI
1
6
PC
H
←
(SP + 1), PC
L
←
(SP),
PSW
←
(SP + 2), SP
←
SP + 3
R
R
R
Call/return
RETB
1
6
PC
H
←
(SP + 1), PC
L
←
(SP),
PSW
←
(SP + 2), SP
←
SP + 3
R
R
R
PSW
1
2
(SP
1)
←
PSW, SP
←
SP
1
PUSH
rp
1
4
(SP
1)
←
rp
H
, (SP
2)
←
rp
L
,
SP
←
SP
2
PSW
1
2
PSW
←
(SP), SP
←
SP + 1
R
R
R
POP
rp
1
4
rp
H
←
(SP + 1), rp
L
←
(SP),
SP
←
SP + 2
SP, #word
4
10
SP
←
word
SP, AX
2
8
SP
←
AX
Stack
manipulate
MOVW
AX, SP
2
8
AX
←
SP
!addr16
3
6
PC
←
addr16
$addr16
2
6
PC
←
PC + 2 + jdisp8
Unconditional
branch
BR
AX
2
8
PCH
←
A, PC
L
←
X
BC
$addr16
2
6
PC
←
PC + 2 + jdisp8 if CY = 1
BNC
$addr16
2
6
PC
←
PC + 2 + jdisp8 if CY = 0
BZ
$addr16
2
6
PC
←
PC + 2 + jdisp8 if Z = 1
Conditional
branch
BNZ
$addr16
2
6
PC
←
PC + 2 + jdisp8 if Z = 0
Notes 1.
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
When an area except the internal high-speed RAM area is accessed
Remarks 1.
One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the processor clock
control register (PCC).
2.
This clock cycle applies to the internal ROM program.