參數(shù)資料
型號: PD75104
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機(jī)
文件頁數(shù): 28/70頁
文件大?。?/td> 485K
代理商: PD75104
μ
PD75104, 75106, 75108
28
5.8
BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this
buffer is very useful for processing long data in bit units.
Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 5-7 Bit Sequential Buffer Format
5.9
POWER-ON FLAG (MASK OPTION)
The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal
has been generated (see Fig. 8-1).
The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation
instruction. However, it cannot be set by the SET1 instruction.
6. INTERRUPT FUNCTIONS
The
μ
PD75108 has 7 different interrupt sources and can perform multiplexed interrupt processing with
priority assigned.
In addition to that, the
μ
PD75108 is also provided with two types of edge detection testable inputs.
The interrupt control circuit of the
μ
PD75108 has these functions:
Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by
using the interrupt enable flag (IExxx) and interrupt master enable flag (IME).
The interrupt start address can be arbitrarily set.
Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS).
Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of
software).
Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
Address bit
Symbol
L register
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
L = F
L = C L = B
L = 8 L = 7
L = 4 L = 3
L = 0
BSB3
BSB2
BSB1
BSB0
DECS L
INCS L
FC3H
FC2H
FC1H
FC0H
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