參數(shù)資料
型號(hào)： PD050VX2
廠商： AZ Displays, Inc.
英文描述： TECHNICAL SPECIFICATION
中文描述： 技術(shù)規(guī)格
文件頁(yè)數(shù)： 8/27頁(yè)
文件大?。?/td> 541K
代理商： PD050VX2
PD050VX2
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
Ltd.
Page:8
Note 5-1: Gate off voltage, V
EE
=-10V.
Note 5-2: Gate on voltage, V
GG
=19V.
Note 5-3: Select up or down shift
U/D
STVU
1
0
Input
Note 5-4: Gate driver shift clock
Note 5-5: When OE is connected to high “1”, the driver outputs are disabled (Gate output =
V
EE
). Under this condition, the operation of registers will not be affected.
Note 5-6: Select left or right shift
R/L
DIO1
DIO2
Shift
1
Input
Hi-Z
Left to right
0
Hi-Z
Input
Right to left
Note 5-7: Latch the polarity of outputs and switch the new data to outputs. At the rising
edge (LD), latch the “POL” signal to control the polarity of the outputs.
Note 5-8: Control whether the Data R0~G5 are inverted or not. (PVI suggests connecting
to GND) When “REV=1”, these data will be inverted.
EX: “00””3F”, “07”
”38”, “15”
”2A”
Note 5-9: Polarity selector for dot-inversion control. Available at the rising edge of LD.
When POL=1: Even outputs range from V1~V7, and Odd outputs range from
V8~V14; When POL=0: Even outputs range from V8~V14, and Odd outputs
range from V1~V7.
STVD
Input
Hi-Z
Shift
Hi-Z
Down to Up
Up to Down
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