參數(shù)資料
型號(hào)： PCM3794RHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 21/67頁(yè)
文件大?。?/td> 1417K
代理商： PCM3794RHBR
www.ti.com
R0002-02
M: Master Device S: Slave Device St: Start Condition
Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge
W: Write R: Read
Transmitter
M
S
Data Type
St
Slave Address
W
ACK
M
Reg Address
M
Sr
M
Slave Address
S
ACK
M
R
S
ACK
M
Sp
M
NACK
S
Read Data
Timing Diagram
SDA
SCL
t(BUF)
t(D-SU)
t(D-HD)
Start
t(LOW)
t(S-HD)
t(SCL-F)
t(SCL-R)
t(HI)
t(RS-SU)
t(RS-HD)
t(SDA-F)
t(SDA-R)
t(P-SU)
Stop
t(SP)
T0050-03
SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
Figure 34. Read Operation
PARAMETERS
CONDITIONS
MIN
MAX
UNIT
fSCL
SCL clock frequency
Standard
100
kHz
t(BUF)
Bus free time between a STOP and START condition
Standard
4.7
s
t(LOW)
Low period of the SCL clock
Standard
4.7
s
t(HI)
High period of the SCL clock
Standard
4
s
t(RS-SU)
Setup time for START condition
Standard
4.7
s
t(S-HD)
Hold time for START condition
Standard
4
s
t(D-SU)
Data setup time
Standard
250
ns
t(D-HD)
Data hold time
Standard
0
900
ns
t(SCL-R)
Rise time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SCL-R1)
Rise time of SCL signal after a repeated START condition and
Standard
20 + 0.1 CB
1000
ns
after an acknowledge bit
t(SCL-F)
Fall time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-R)
Rise time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-F)
Fall time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(P-SU)
Setup time for STOP condition
Standard
4
s
CB
Capacitive load for SDA and SCL line
400
pF
t(SP)
Pulse duration of suppressed spike
25
ns
Figure 35. I2C Interface Timing
28
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