參數(shù)資料
型號: PCM3168ATPAPRQ1
廠商: Texas Instruments
文件頁數(shù): 27/68頁
文件大小: 0K
描述: IC 24-BIT AUDIO CODEC 64-HTQFP
標準包裝: 1,000
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 6 / 8
三角積分調(diào)變:
S/N 比,標準 ADC / DAC (db): 107 / 112(差分),104 / 112(單端)
動態(tài)范圍,標準 ADC / DAC (db): 107 / 112(差分),104 / 112(單端)
電壓 - 電源,模擬: 4.5 V ~ 5.5 V
電壓 - 電源,數(shù)字: 3 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-HTQFP(10x10)
包裝: 帶卷 (TR)
TIMING CHARACTERISTICS: FOUR-WIRE
MS
1.4V
0.5 VDD
t
MSH
t
MDD
t
MDR
LSB(D0)
Hi-Z
t
MSS
t
MCH
t
MCL
t
MDD
t
MDS
ADR0
MSB(R/ )
W
MSB(D7)
Hi-Z
MC
MDI
MDO
t
MDH
t
MCY
t
MHH
MSB(D7)
TWO-WIRE (I
2C) SERIAL CONTROL
MSB
LSB
1
0
1
ADR1
ADR0
R/W
www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008
(1) These timing parameters are critical for proper control port operation.
Figure 50. Four-Wire Serial Control Interface Timing(1)
Timing Requirements for Figure 50(1)
PCM3168A, PCM3168A-Q1
SYMBOL
PARAMETER
MIN
MAX
UNIT
tMCY
MC pulse cycle time
100
ns
tMCL
MC low-level time
40
ns
tMCH
MC high-level time
40
ns
tMHH
MS high-level time
tMCY
ns
tMSS
MS falling edge to MC rising edge
30
ns
tMSH
MS rising edge from MC rising edge for LSB
15
ns
tMDH
MDI hold time
15
ns
tMDS
MDI setup time
15
ns
tMDD
MDO enable or delay time from MC falling edge
0
30
ns
tMDR
MDO disable time from MS rising edge
0
30
ns
(1)
These timing parameters are critical for proper control port operation.
The PCM3168A and PCM3168A-Q1 support an I2C-compatible serial bus and data transmission protocol for fast
mode configured as a slave device. This protocol is explained in the I2C specification, version 2.0.
The PCM3168A and PCM3168A-Q1 have a 7-bit slave address, as shown in Figure 51. The first five bits are the
most significant bits (MSB) of the slave address and are factory-preset to 10001. The next two bits of the
address byte are selectable bits that can be set by MS/ADR0/MD0 and MDO/ADR1/MD1. A maximum of four
PCM3168A and PCM3168A-Q1s can be connected on the same bus at any one time. Each PCM3168A and
PCM3168A-Q1 respond when it receives its own slave address.
Figure 51. Slave Address
Copyright 2008, Texas Instruments Incorporated
33
Product Folder Link(s): PCM3168A PCM3168A-Q1
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