
7
PCM1732
SYSTEM CLOCK
The system clock for PCM1732 must be either 256f
S
, 384f
S
,
512f
S
or 768f
S
, where f
S
is the audio sampling frequency
(typically 32kHz, 44.1kHz, 48kHz, 88kHz, or 96kHz). A
768f
S
system clock is not supported for 88.2kHz and 96kHz
sampling frequencies.
The system clock can be either a crystal oscillator placed
between XTI (pin 5) and XTO (pin 6), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
PCM1732 has a system clock detection circuit which auto-
matically senses if the system clock is operating at 256f
S
~
768f
S
. The system clock should be synchronized with the
left/right clock (LRCIN, pin 1). LRCIN operates at the sam-
pling frequency (f
S
). In the event these clocks are not
synchronized, the PCM1732 can compensate for the phase
difference internally. If the phase difference between left-
right and system clocks is greater than 6-bit clocks (BCKIN),
the synchronization is performed internally. While the syn-
chronization is processing, the analog output is forced to a
DC level at bipolar zero. The synchronization typically
occurs in less than 1 cycle of LRCIN.
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING RATE FREQUENCY (f
S
)
256f
S
384f
S
512f
S
768f
S
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
8.1920
11.2896
12.2880
22.5792
24.5760
12.2880
16.9340
18.4320
33.8688
(1)
36.8640
(1)
16.3840
22.5792
24.5760
45.1584
(1)
49.1520
(1)
24.5760
33.8688
(1)
36.8640
(1)
—
—
NOTE: (1) The internal crystal oscillator frequency cannot be larger than 24.576MHz.
TABLE I. Typical System Clock Frequencies.
Typical input system clock frequencies to the PCM1732 are
shown in Table I and external input clock timing require-
ments are shown in Figure 2.
FIGURE 1. System Clock Connection.
FIGURE 2. XTI Clock Timing.
DATA INTERFACE FORMATS
Digital audio data is interfaced to the PCM1732 on pin 1
(LRCIN), pin 2 (DIN), and pin 3 (BCKIN). The PCM1732
can accept standard, I
2
S, and left-justified data formats.
Figure 3 illustrates acceptable input data formats. Figure 4
shows required timing specifications for digital audio data.
Reset
PCM1732 has both an internal power-on reset circuit and a
RST pin (pin 22), which accepts an external reset when RST
= LOW. For internal power-on reset, initialization (reset) is
done automatically at power-on when V
DD
> 2.2V (typical).
During internal reset = LOW, the output of the DAC is
invalid and the analog outputs are forced to V
CC
/2. Figure
5 illustrates the timing of the internal power-on reset.
PCM1732 accepts an external forced reset when RST =
LOW. When RST = LOW, the output of the DAC is invalid
and the analog outputs are forced to V
CC
/2 after internal
initialization (1024 system clocks count after RST = HIGH.)
Figure 6 illustrates the timing of the RST pin.
Zero Out (pin 21)
Zero is an open drain output. If the input data is continuously
zero for 65,536 cycles of BCKIN, an internal FET is switched
to “ON” and the drain of the internal FET is switched to
ground. The zero detect function is available in both software
mode and hardware mode.
System Clock
(256/384/512/768f
S
)
External Clock Input
CLKO
XTI
XTO
4
5
6
PCM1732
System Clock
Buffer Out
Crystal Resonator Oscillation
CLKO
XTI
XTO
4
5
6
PCM1732
XTAL
C
1
C
2
C
1
C
2
: 10pF ~ 30pF
Buffer
t
SCKH
System Clock Pulse Width HIGH: t
SCKIH
: 8ns (min)
System Clock Pulse Width LOW: t
SCKIL
: 8ns (min)
System Clock Duty: 40% to 60%
t
SCKL
70% of V
DD
30% of V
DD
H
L
XTI