參數(shù)資料
型號： PCM1723
英文描述： Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE PLL
中文描述： 立體聲音頻數(shù)字模擬轉(zhuǎn)換器，具有可編程鎖相環(huán)
文件頁數(shù)： 9/15頁
文件大?。?/td> 218K
代理商： PCM1723
9
PCM1723
loaded into AL0:AL7, but it will not affect the attenuation
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation.
Attenuation Level (ATT) can be controlled as following
Resistor set AL (R) (7:0).
AL (R) (7:0)
00h
01h
.
.
.
FEh
FFh
ATT LEVEL
–
∞
dB (Mute)
–48.16dB
.
.
.
–0.07dB
0dB
REGISTER 1 (A1 = 0, A0 = 1)
MAPPING OF PROGRAM REGISTERS
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MODE0
res
res
res
res
res
A1
A0
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
MODE1
res
res
res
res
res
A1
A0
LDR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
MODE2
res
res
res
res
res
A1
A0
PL3
PL2
PL1
PL0
IW1
IW0
OPE
DEM
MUT
MODE3
res
res
res
res
res
A1
A0
IZD
SF1
SF0
DSR1
DSR0
SYS
ATC
LRP
I
2
S
PROGRAM REGISTER BIT MAPPING
PCM1723’s special functions are controlled using four pro-
gram registers which are 16 bits long. These registers are all
loaded using MD. After the 16 data bits are clocked in, ML
is used to latch in the data to the appropriate register. Table
IV shows the complete mapping of the four registers and
Figure 8 illustrates the serial interface timing.
REGISTER
NAME
BIT
NAME
DESCRIPTION
Register 0
AL (7:0)
LDL
A (1:0)
Res
DAC Attenuation Data for Lch
Attenuation Data Load Control for Lch
Register Address
Reserved
Register 1
AR (7:0)
LDL
A (1:0)
Res
DAC Attenuation Data for Rch
Attenuation Data Load Control for Rch
Register Address
Reserved
Register 2
MUT
DEM
OPE
IW (1:0)
PL (3:0)
A (1:0)
res
Left and Right DACs Soft Mute Control
De-emphasis Control
Left and Right DACs Operation Control
Input Audio Data Bit Select
Output Mode Select
Register Address
Reserved
Register 3
I
2
S
LRP
ATC
SYS
Audio Data Format Select
Polarity of LRCIN (pin 7) Select
Attenuator Control
System Clock Select
Double Sampling Rate Select
Sampling Rate Select
Infinite Zero Detection Circuit Control
Register Address
Reserved
DSR (1:0)
SF (1:0)
IZD
A (1:0)
Res
TABLE IV. Internal Register Mapping.
REGISTER 0 (A1 = 0, A0 = 0)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res res res
res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register 0 is used to control left channel attenuation. Bits
0 - 7 (AL0 - AL7) are used to determine the attenuation
level. The level of attenuation is given by:
ATT = [20 log10 (ATT_DATA/255)] dB
ATTENUATION DATA LOAD CONTROL
Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
B15 B14 B13 B12 B11 B10 B9 B8
B7
B6
B5
B4
B3
B2
B1
B0
res res res res res
A1 A0
LDR
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0 - 7 (AR0 - AR7) control the level of
attenuation.
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res res
res
res A1
A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEMMUTE
Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and output format. Bit 0 is used
for soft mute: a “HIGH” level on bit 0 will cause the output
to be muted (this is ramped down in the digital domain, so
no “click” is audible). Bit 1 is used to control de-emphasis.
A “LOW” level on bit 1 disables de-emphasis, while a
“HIGH” level enables de-emphasis.
Bit 2, (OPE) is used for operational control. Table V illus-
trates the features controlled by OPE.
SOFTWARE MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Forced to BPZ
(1)
Controlled by IZD
Normal
Enabled
Enabled
Enabled
Enabled
OPE = 1
OPE = 0
TABLE V. Operation Enable (OPE) Function.
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參數(shù)描述
PCM1723E 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Ster DAC w/Prog PLL RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1723E/2K 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Ster DAC w/Prog PLL RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1723E/2KG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Ster DAC w/Prog PLL RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1723EG 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:
PCM1723EG/2K 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL-TO-ANALOG CONVERTER With Programmable PLL
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