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參數(shù)資料
| 型號： | PCM1602APTG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 13/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 24BIT 6CH 192KHZ 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 6 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 240mW |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 192k |
| 配用： | DEM-DAI1602-ND - EVAL FIXTURE FOR PCM1602 |
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t(MCH)
1.4 V
ML
t(MLS)
LSB
1.4 V
t(MCL)
t(MHH)
t(MLH)
t(MCY)
t(MDH)
t(MDS)
MC
MDI
LSB
MDI
T0013-05
LSB
50% of VDD
MDO
t(MOS)
1.4 V
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
www.ti.com
AUTO-INCREMENT READ OPERATION
The auto-increment read function allows for multiple registers to be read sequentially. The auto-increment read
function is enabled by setting the INC bit of control register 11 to 1. The sequence always starts with the register
indexed by the REG[6:0] bits in control register 11, and ends by the ML setting to 1 after MC clock cycle for the
least-significant bit of last register.
Figure 26 shows the timing of the auto-increment read operation. The operation begins by writing control register
11, setting INC to 1, and setting REG[6:0] to the first register to be read in the sequence. The actual read
operation starts on the next HIGH-to-LOW transition of the ML pin.
The read cycle starts by setting the R/W bit of the control word to 1, and setting all of the IDX[6:0] bits to 0. All
subsequent bits input on MDI are ignored while ML is set to 0. For the first eight clocks of the read cycle, MDO is
set to the high-impedance state. This is followed by a sequence of 8-bit words, each corresponding to the data
contained in control registers N through Y, where N is defined by the REG[6:0] bits in control register 11, and
where Y is the last register to be read. The read cycle is completed when ML is set to 1, immediately after the
MC clock cycle for the least-significant bit of the last register has completed. If ML is held low and the MC clock
continues beyond the last physical register (register 12), the read operation returns to control register 1 and
subsequent control registers, continuing until ML is set to 1.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 27 shows a detailed timing diagram for the serial control interface. Pay special attention to the setup and
hold times, as well as t(MLS) and t(MLH), which define minimum delays between the edges of the ML and MC
clocks. These timing parameters are critical for proper control-port operation.
SYMBOL
PARAMETER
MIN
MAX
UNITS
t(MCY)
MC pulse cycle time
100
ns
t(MCL)
MC low-level time
50
ns
t(MCH)
MC high-level time
50
ns
t(MHH)
ML high-level time
300
ns
t(MLS)
ML falling edge to MC rising edge
20
ns
t(MLH)
ML hold time
20
ns
t(MDH)
MDI hold time
15
ns
t(MDS)
MDL setup time
20
ns
t(MOS)
MC falling edge to MDO stable
30
ns
(1)
MC rising edge for LSB to ML rising edge.
Figure 27. Control Interface Timing
20
Copyright 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): PCM1602A
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