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參數(shù)資料
| 型號： | PCM1601Y |
| 英文描述： | 24-Bit, 96kHz Sampling, 6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位，96kHz采樣，6通道，增強的多級，Δ-Σ數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 253K |
| 代理商： | PCM1601Y |
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14
PCM1600, PCM1601
corresponds to the 8 data bits of the register indexed by the
REG[6:0] bits of Control Register 11. The Read cycle is
completed when ML is set to ‘1’, immediately after the MC
clock cycle for the least significant bit of indexed control
register has completed.
AUTO-INCREMENT READ OPERATION
The Auto-Increment Read function allows for multiple reg-
isters to be read sequentially. The Auto-Increment Read
function is enabled by setting the INC bit of Control Register
11 to ‘1’. The sequence always starts with Register 1, and
ends with the register indexed by the REG[6:0] bits in
Control Register 11.
Figure 9 shows the timing for the Auto-Increment Read
operation. The operation begins by writing Control Register
11, setting INC to ‘1’ and setting REG[6:0] to the last
register to be read in the sequence. The actual Read opera-
tion starts on the next HIGH to LOW transition of the ML
50% of V
DD
50% of V
DD
50% of V
DD
50% of V
DD
ML
MC
MDI
MDO
t
MLS
t
MCH
t
MCY
t
MOS
t
MDS
t
MCH
t
MCL
t
MHH
t
MLH
LSB
LSB
pin. The Read cycle starts by setting the R/W bit of the
control word to ‘1’, and setting all of the IDX[6:0] bits to
‘0.’. All subsequent bits input on the MDI are ignored while
ML is set to ‘0.’ For the first 8 clocks of the Read cycle,
MDO is set to a high-impedance state. This is followed by
a sequence of 8-bit words, each corresponding the data
contained in Control Registers 1 through N, where N is
defined by the REG[6:0] bits in Control Register 11. The
Read cycle is completed when ML is set to ‘1’, immediately
after the MC clock cycle for the least significant bit of
Control Register N has completed.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 10 shows a detailed timing diagram for the Serial
Control interface. Pay special attention to the setup and hold
times, as well as t
MLS
and t
MLH
, which define minimum delays
between edges of the ML and MC clocks. These timing
parameters are critical for proper control port operation.
SYMBOL
PARAMETER
MIN
MAX
UNITS
t
MCY
t
MCL
t
MCH
t
MHH
t
MLS
t
MLH
t
MDI
t
MDS
t
MOS
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
ML High Level Time
ML Falling Edge to MC Rising Edge
ML Hold Time
(1)
Hold Time
MDL Set Up Time
MC Falling Edge to MDSO Stable
100
50
50
300
20
20
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
NOTE: (1) MC rising edge for LSB to ML rising edge.
FIGURE 10. Control Interface Timing.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCM1601Y/1K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:D/A CONVERTER |
| PCM1602 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 192kHz Sampling, 6-Channel, Enhanced Multilevel, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| PCM1602 CL001 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 16AWG CLR 1000' |
| PCM1602 CL005 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 16AWG CLR 100' |
| PCM1602A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 192-kHz Sampling, 6-Channel, Enhanced Multilevel, Delta-Sigma Digital-to-Analog Converter |
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