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| 型號(hào)： | PCI6611 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER |
| 中文描述： | 雙/單插槽CardBus和UltraMedia控制器 |
| 文件頁數(shù)： | 92/204頁 |
| 文件大?。?/td> | 860K |
| 代理商： | PCI6611 |
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416
Table 47. Bridge Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
5
MABTMODE
RW
Master abort mode. This bit controls how the PCI6x21/PCI6x11 controller responds to a master abort when
the PCI6x21/PCI6x11 controller is an initiator on the CardBus interface. This bit is common between each
socket.
0 = Master aborts not reported (default).
1 = Signal target abort on PCI and signal SERR, if enabled.
4
RSVD
R
This bit returns 0 when read.
3
VGAEN
RW
VGA enable. This bit affects how the PCI6x21/PCI6x11 controller responds to VGA addresses. When this
bit is set, accesses to VGA addresses are forwarded.
2
ISAEN
RW
ISA mode enable. This bit affects how the PCI6x21/PCI6x11 controller passes I/O cycles within the
64-Kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI6x21/PCI6x11
controller does not forward the last 768 bytes of each 1K I/O range to CardBus.
1
CSERREN
RW
CSERR enable. This bit controls the response of the PCI6x21/PCI6x11 controller to CSERR signals on
the CardBus bus. This bit is separate for each socket.
0 = CSERR is not forwarded to PCI SERR (default)
1 = CSERR is forwarded to PCI SERR.
0
CPERREN
RW
CardBus parity error response enable. This bit controls the response of the PCI6x21/PCI6x11 to CardBus
parity errors. This bit is separate for each socket.
0 = CardBus parity errors are ignored (default).
1 = CardBus parity errors are reported using CPERR.
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI offset 80h, See Section 4.29). When bit 5 is 0, this register is read/write; when bit 5
is 1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Subsystem vendor ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subsystem vendor ID
40h (Functions 0, 1)
Read-only, (Read/Write when bit 5 in the system control register is 0)
0000h
4.27 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0, this register is read/write; when bit 5 is
1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
If an EEPROM is present, then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after a reset.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Subsystem ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subsystem ID
42h (Functions 0, 1)
Read-only, (Read/Write when bit 5 in the system control register is 0)
0000h
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