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參數(shù)資料
| 型號： | PCI6515ZHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
| 中文描述： | 單插槽CardBus控制器，專用智能卡插槽 |
| 文件頁數(shù)： | 44/148頁 |
| 文件大?。?/td> | 760K |
| 代理商： | PCI6515ZHK |
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SDA
SCL
Start
Condition
Stop
Condition
Change of
Data Allowed
Data Line Stable,
Data Valid
Figure 36. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 37
illustrates the acknowledge protocol.
SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 37. Serial-Bus Protocol Acknowledge
The PCI6515 controller is a serial bus master; all other devices connected to the serial bus external to the PCI6515
controller are slave devices. As the bus master, the PCI6515 controller drives the SCL clock at nearly 100 kHz during
bus cycles and places SCL in a high-impedance state (zero frequency) during idle states.
Typically, the PCI6515 controller masters byte reads and byte writes under software control. Doubleword reads are
performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software
control. See Section 3.6.4,
Serial-Bus EEPROM Application
, for details on how the PCI6515 controller automatically
loads the subsystem identification and other register defaults through a serial-bus EEPROM.
Figure 38 illustrates a byte write. The PCI6515 controller issues a start condition and sends the 7-bit slave device
address and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The slave
device acknowledges if it recognizes the address. If no acknowledgment is received by the PCI6515 controller, then
an appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see Section 4.49). The word
address byte is then sent by the PCI6515 controller, and another slave acknowledgment is expected. Then the
PCI6515 controller delivers the data byte MSB first and expects a final acknowledgment before issuing the stop
condition.
S
b6
b4
b5
b3 b2 b1 b0
0
b7 b6 b5
b4 b3
b2
b1 b0
A
A
Slave Address
Word Address
R/W
S/P = Start/Stop Condition
A = Slave Acknowledgement
b7
b6
b4
b5
b3 b2 b1 b0
A
P
Data Byte
Figure 38. Serial-Bus Protocol—Byte Write
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