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參數(shù)資料
| 型號(hào)： | PCI6515 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
| 中文描述： | 單插槽CardBus控制器，專(zhuān)用智能卡插槽 |
| 文件頁(yè)數(shù)： | 27/148頁(yè) |
| 文件大小： | 760K |
| 代理商： | PCI6515 |
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211
Table 28. PCI Interface Control Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
DEVSEL
U06
I/O
PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator
on the bus, the controller monitors DEVSEL until a target responds. If no target responds before timeout occurs,
then the controller terminates the cycle with an initiator abort.
FRAME
R06
I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus
transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted,
the PCI bus transaction is in the final data phase.
GNT
L02
I
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the controller access to the PCI bus after the current
data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus
parking algorithm.
IDSEL
N05
I
Initialization device select. IDSEL selects the controller during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines on the PCI bus.
IRDY
V05
I/O
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until
IRDY and TRDY are both sampled asserted, wait states are inserted.
PERR
R07
I/O
PCI parity error indicator. PERR is driven by a PCI controller to indicate that calculated parity does not match
PAR when PERR is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4).
REQ
L03
O
PCI bus request. REQ is asserted by the controller to request access to the PCI bus as an initiator.
SERR
W06
O
PCI system error. SERR is an output that is pulsed from the controller when enabled through bit 8 of the
command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The controller need
not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register, this signal
also pulses, indicating that an address parity error has occurred on a CardBus interface.
STOP
V06
I/O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support
burst data transfers.
TRDY
W05
I/O
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until
both IRDY and TRDY are asserted, wait states are inserted.
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參數(shù)描述 |
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| PCI6515A | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Single Socket CardBus Controller with Dedicated Smart Card Socket |
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| PCI6515ZHK | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
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