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    參數(shù)資料
    型號(hào): PCF8584
    廠商: NXP Semiconductors N.V.
    英文描述: IIC-bus controller(IIC總線控制器)
    中文描述: IIC總線控制器(國(guó)際進(jìn)口總線控制器)
    文件頁(yè)數(shù): 6/40頁(yè)
    文件大?。?/td> 224K
    代理商: PCF8584
    1997 Oct 21
    6
    Philips Semiconductors
    Product specification
    I
    2
    C-bus controller
    PCF8584
    6
    FUNCTIONAL DESCRIPTION
    6.1
    General
    The PCF8584 acts as an interface device between
    standard high-speed parallel buses and the serial I
    2
    C-bus.
    On the I
    2
    C-bus, it can act either as master or slave.
    Bidirectional data transfer between the I
    2
    C-bus and the
    parallel-bus microcontroller is carried out on a byte-wise
    basis, using either an interrupt or polled handshake.
    Interface to either 80XX-type (e.g. 8048, 8051, Z80) or
    68000-type buses is possible. Selection of bus type is
    automatically performed (see Section 6.2).
    Fig.2 Pin configuration.
    handbook, halfpage
    CLK
    SDA or SDA OUT
    SCL or SCL IN
    A0
    DB0
    DB1
    DB2
    VSS
    VDD
    DB7
    DB6
    DB5
    DB4
    DB3
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    20
    19
    18
    17
    16
    15
    14
    13
    12
    11
    PCF8584
    MLA012 - 1
    IACK or SDA IN
    INT or SCL OUT
    RESET / STROBE
    CS
    RD (DTACK)
    WR (R/W)
    (1)
    (1)
    (1) Pin mnemonics between parenthesis indicate the 68000 mode
    pin designations.
    Table 1
    Control signals utilized by the PCF8584 for
    microcontroller/microprocessor interfacing
    The structure of the PCF8584 is similar to that of the
    I
    2
    C-bus interface section of the Philips’
    MABXXXX/PCF84(C)XX-series of microcontrollers, but
    with a modified control structure. The PCF8584 has five
    internal register locations. Three of these (own address
    register S0', clock register S2 and interrupt vector S3) are
    used for initialization of the PCF8584. Normally they are
    only written once directly after resetting of the PCF8584.
    The remaining two registers function as double registers
    (data buffer/shift register S0, and control/status
    register S1) which are used during actual data
    transmission/reception. By using these double registers,
    which are separately write and read accessible, overhead
    for register access is reduced. Register S0 is a
    combination of a shift register and data buffer.
    Register S0 performs all serial-to-parallel interfacing with
    the I
    2
    C-bus.
    Register S1 contains I
    2
    C-bus status information required
    for bus access and/or monitoring.
    6.2
    Interface Mode Control (IMC)
    Selection of either an 80XX mode or 68000 mode
    interface is achieved by detection of the first WR-CS signal
    sequence. The concept takes advantage of the fact that
    the write control input is common for both types of
    interfaces. An 80XX-type interface is default. If a
    HIGH-to-LOW transition of WR (R/W) is detected while CS
    is HIGH, the 68000-type interface mode is selected and
    theDTACK output is enabled. Care must be taken thatWR
    and CS are stable after reset.
    TYPE
    R/W
    WR
    R
    DTACK
    IACK
    8048/
    8051
    68000
    Z80
    no
    yes
    yes
    no
    no
    yes
    no
    no
    yes
    no
    yes
    yes
    no
    yes
    yes
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