參數(shù)資料
型號(hào): PCF8531
廠商: NXP Semiconductors N.V.
英文描述: 34×128 pixel matrix driver(34×128 像素矩陣驅(qū)動(dòng)器)
中文描述: 34 × 128像素矩陣驅(qū)動(dòng)器(34 × 128像素矩陣驅(qū)動(dòng)器)
文件頁(yè)數(shù): 24/44頁(yè)
文件大小: 212K
代理商: PCF8531
2000 Feb 11
24
Philips Semiconductors
Product specification
34
×
128 pixel matrix driver
PCF8531
13 AC CHARACTERISTICS
V
DD1
= 1.8 to 5.5 V; V
DD2
and V
DD3
= 2.5 to 4.5 V; V
SS1
and V
SS2
= 0 V; V
DD1
to V
DD3
V
LCD
9.0 V;
T
amb
=
40 to +85
°
C; unless otherwise specified.
Notes
1.
2.
3.
f
frame
= f
clk(ext)
/480; f
OSC
/480.
For t
W(RESL)
> 3 ns a reset may be generated.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
C
b
= total capacitance of one bus line in pF.
4.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
frame
f
OSC
f
clk(ext)
t
W(RESL)
t
SU;RESL
Serial-bus interface;
note 3
LCD frame frequency (internal clock)
oscillator frequency (not available at any pin)
external clock frequency
reset LOW pulse width
reset LOW pulse set-up time after Power-on
V
DD
= 3.0 V; note 1 40
66
34
135
65
65
30
Hz
kHz
kHz
ns
μ
s
20
20
300
note 2
f
SCL
t
SCLL
t
SCLH
t
SU;DAT
t
HD;DAT
t
r
t
f
C
b
t
SU;STA
t
HD;STA
t
SU;STO
t
SW
t
BUF
SCL clock frequency
SCL clock LOW period
SCL clock HIGH period
data set-up time
data hold time
SCL, SDA rise time
SCL, SDA fall time
capacitive load represented by each bus line
set-up time for a repeated START condition
start condition hold time
set-up time for STOP condition
tolerable spike width on bus
bus free time between a STOP and START
condition
0
1.3
0.6
100
0
20 + 0.1C
b
20 + 0.1C
b
0.6
0.6
0.6
1.3
400
0.9
300
300
400
50
kHz
μ
s
μ
s
ns
μ
s
ns
ns
pF
μ
s
μ
s
μ
s
ns
μ
s
note 4
note 4
handbook, full pagewidth
MGS476
tW(RESL)
tSU;RESL
VIL
VDD
RES
Fig.16 Reset timing.
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