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參數(shù)資料
| 型號： | PCF52274CLU120 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 14/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32-BIT W/LCD TOUCH 176-LQFP |
| 標準包裝： | 40 |
| 系列： | MCF5227x |
| 核心處理器： | Coldfire V2 |
| 芯體尺寸： | 32-位 |
| 速度： | 120MHz |
| 連通性： | CAN，EBI/EMI，I²C，SPI，SSI，UART/USART，USB OTG |
| 外圍設備： | DMA，LCD，PWM，WDT |
| 輸入/輸出數(shù)： | 47 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.4 V ~ 1.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 176-LQFP |
| 包裝： | 托盤 |
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Electrical Characteristics
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
21
5.7
External Interface Timing Specifications
5.7.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 66MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the Flexbus output
clock, FB_CLK. All other timing relationships can be derived from these values.
Conversion Time
tADC
15
—
32
tAIC
cycles
Sample Time
tADS
3—
20
tAIC
cycles
Multiplexer Settling Time
tAMS
——
3
tAIC
cycles
Zero-scale Error
ZE
—
±4
±12
Full-scale Error
FE
—
±320
±370
lsb1
Input Capacitance
CAIN
——34
pF
1 A least significant bit (lsb) is a unit of voltage equal to the smallest resolution of the ADC. This unit of measure approximately
relates the error voltage to the observed error in conversion (code error), and is useful for systemic errors such as differential
non-linearity. A 2.56-V input on an ADC with ± 3 lsb of error could read between 0x1FD and 0x203. This unit is by far the most
common terminology and will be the preferred unit used for error representation.
A bit is a unit equal to the log (base2) of the error voltage normalized to the resolution of the ADC. An error of N bits
corresponds to 2N lsb of error. This measure is easily confused with lsb and is hard to extrapolate between integer values.
Table 13. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
—
83.33
MHz
fsys/2
FB1
Clock Period (FB_CLK)
tFBCK
12.0
—
ns
tcyc
FB2
Address, Data, and Control Output Valid (FB_A[23:0], FB_D[31:0],
FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0] and FB_OE)
tFBCHDCV
—7.0
ns
1
FB3
Address, Data, and Control Output Hold (FB_A[23:0], FB_D[31:0],
FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0], and FB_OE)
tFBCHDCI
1—
ns
1, 2
Table 12. ASP Electrical Characteristics (continued)
Characteristic
Symbol
Min
Typical
Max
Unit
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