The average chip-junction" />
參數(shù)資料
型號(hào)： PCF51AC128ACLKE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 11/42頁(yè)
文件大?。?/td> 0K
描述： MCU 8BIT 128K FLASH 80-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： MCF51AC
核心處理器： Coldfire V1
芯體尺寸： 32-位
速度： 50MHz
連通性： CAN，I²C，SCI，SPI
外圍設(shè)備： LVD，PWM，WDT
輸入/輸出數(shù)： 69
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 24x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-LQFP
包裝： 托盤
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor
19
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)
Eqn. 1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K (TJ + 273C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)
2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
2.4
Electrostatic Discharge (ESD) Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
1 Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance
2 Junction to Ambient Natural Convection
3 1s — Single layer board, one signal layer
4 2s2p — Four layer board, 2 signal and 2 power layers
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