參數(shù)資料
型號: PCF51AC128ACFUE
廠商: Freescale Semiconductor
文件頁數(shù): 41/42頁
文件大?。?/td> 0K
描述: MCU 8BIT 128K FLASH 64-QFP
標準包裝: 84
系列: MCF51AC
核心處理器: Coldfire V1
芯體尺寸: 32-位
速度: 50MHz
連通性: CAN,I²C,SCI,SPI
外圍設備: LVD,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 20x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-QFP
包裝: 托盤
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
MCF51AC256 Family Configurations
Freescale Semiconductor
8
— Trimmable internal reference allows 0.2% resolution and 2% deviation
Analog-to-digital converter (ADC)
— 24 analog inputs with 12 bits resolution
— Output formatted in 12-, 10- or 8-bit right-justified format
— Single or continuous conversion (automatic return to idle after single conversion)
— Operation in low-power modes for lower noise operation
— Asynchronous clock source for lower noise operation
— Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable
value
— On-chip temperature sensor
Flexible timer/pulse-width modulators (FTM)
— 16-bit Free-running counter or a counter with initial and final value. The counting can be up
and unsigned, up and signed, or up-down and unsigned
— Up to 6 channels, and each channel can be configured for input capture, output compare or
edge-aligned PWM mode, all channels can be configured for center-aligned PWM mode
– Channels can operate as pairs with equal outputs, pairs with complimentary outputs or
independent channels (with independent outputs)
– Each pair of channels can be combined to generate a PWM signal (with independent control
of both edges of PWM signal)
– Deadtime insertion is available for each complementary pair
— The load of the FTM registers which have write buffer can be synchronized; write protection
for critical registers
— Generation of the triggers to ADC (hardware trigger)
— A fault input for global fault control
— Backwards compatible with TPM
Timer/pulse width modulator (TPM)
— 16-bit free-running or modulo up/down count operation
— Two channels, each channel may be input capture, output compare, or edge-aligned PWM
— One interrupt per channel plus terminal count interrupt
Cyclic redundancy check (CRC) generator
— High speed hardware CRC generator circuit using 16-bit shift register
— CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial
— Error detection for all single, double, odd, and most multi-bit errors
— Programmable initial seed value
Analog comparators (ACMP)
— Full rail to rail supply operation
— Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator
output
— Option to compare to fixed internal bandgap reference voltage
— Option to allow comparator output to be visible on a pin, ACMPxO
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