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參數(shù)資料
| 型號(hào)： | PCF50603HN |
| 廠商： | ST-ERICSSON |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 0.85 MM HEIGHT, SOT-778-1, PLASTIC, HVQFN-48 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 147K |
| 代理商： | PCF50603HN |
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2003 Oct 31
13
Philips Semiconductors
Preliminary specication
Controller for power supply
and battery management
PCF50603
8.1.5
DEBOUNCE FILTERS
Fig.7 is applicable for all debounce filters in the PCF50603.
handbook, full pagewidth
MDB684
tdebounce
falling edge
interrupts
debounced
un-debounced
rising edge
tdebounce
Fig.7 Definition of debounce filter.
The debounced signal keeps the old value until the new value has been stable for at least the applicable debounce time. Any spike (>30 ms) in the
original signal will reset the debounce timer again. This filter suppresses all signal changes that are shorter than the debounce time.
8.2
Serial interface (I2C-bus)
The I2C-bus is the serial interface of the PCF50603.
A detailed description of the I2C-bus specification,
including applications, is given in the brochure: The
I2C-bus and how to use it, order no. 9398 393 40011 or
I2C-bus Peripherals Data Handbook IC12.
8.3
Interrupt controller (INT)
The PCF50603 uses the interrupt controller to indicate to
the system controller if the status of the PCF50603 change
and that an action of the system controller is required.
Interrupts can be generated by several modules of the
PCF50603. The interrupt generator handles all interrupts
with the same priority. Priority setting shall be done by the
system controller software.
There are no timing requirements for interrupt service
response times. All events that require immediate actions
are performed by the PCF50603 without any action by the
system controller.
The function of the interrupt module is to capture, mask
and combine the interrupt signals from the modules that
can generate an interrupt. All interrupts are combined in
the interrupt signal IRQ_N. The IRQ_N signal is
implemented as an open-drain output with an internal
pull-up resistor.
The interrupt module is powered in all states (except
NOPOWER) and retains the register values. Events that
occur in the STANDBY state, are captured and can be
read out by the system controller once the system is in the
ACTIVE state.
The IRQ_N signal is asserted in the ACTIVE state
whenever one or more PCF50603 interrupts are active.
Each interrupt register (8-bits) is cleared when it is read
(R&C) through the I2C-bus interface. New interrupts that
occur during a R&C action are captured in an intermediate
register (see Figs.8 and 9).
All interrupts related to shut-down conditions (LOWBAT,
ONKEY1S and HIGHTMP) are automatically cleared on a
transition from ACTIVE to STANDBY state.
All interrupts can be masked: this effectively prevents that
IRQ_N is asserted for masked interrupts. Masking is
implemented with a mask bit in the mask registers for each
interrupt source. Nevertheless, the interrupt status
registers still provide the actual interrupt status of the
masked interrupts, which allows polling of the interrupt
status registers. Note that if the mask bit is cleared for an
active interrupt, the IRQ_N line goes LOW at the next
falling edge of the output pin CLK32K.
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