參數(shù)資料
型號: PCF2116GHZ
廠商: NXP SEMICONDUCTORS
元件分類: 顯示控制器
英文描述: LCD controller/drivers
中文描述: 32 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-425-1, LQFP-128
文件頁數(shù): 17/64頁
文件大?。?/td> 407K
代理商: PCF2116GHZ
1997 Apr 07
17
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
Fig.11 Relationship between CGRAM addresses and data and display patterns.
handbook, full pagewidth
MGA800 - 1
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
4
3
2
1
0
higher
order
bits
lower
order
bits
lower
order
bits
higher
order
bits
lower
order
bits
higher
order
bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
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1
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0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
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0
0
0
0
0
0
0
0
0
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0
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1
1
1
1
0
0
1
1
0
0
1
1
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1
0
1
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1
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1
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0
0
0
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0
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1
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0
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0
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1
0
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1
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0
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0
1
0
0
0
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1
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1
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1
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1
1
1
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1
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1
1
1
character codes
(DDRAM data)
CGRAM
address
character patterns
(CGRAM data)
character
pattern
example 1
cursor
position
character
pattern
example 2
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with
the cursor. Data in the 8th line will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.11 (bit 4 being at the left end).
As shown in Figs 8 and 11, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1
corresponds to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘Set CGRAM address’ instruction. Bit 6 can be set using the ‘Set DDRAM address’ instruction
or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read busy flag and address’ instruction.
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