參數(shù)資料
型號(hào)： PCF2116AHZ
廠商： NXP SEMICONDUCTORS
元件分類： 顯示控制器
英文描述： JT 66C 66#22D PIN RECP
中文描述： 32 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-425-1, LQFP-128
文件頁(yè)數(shù)： 7/64頁(yè)
文件大?。?/td> 407K
代理商： PCF2116AHZ
1997 Apr 07
7
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
7
PIN FUNCTIONS
7.1
RS: register select (parallel control)
RS selects the register to be accessed for read and write
when the device is controlled by the parallel interface.
RS = logic 0 selects the instruction register for write and
the Busy Flag and Address Counter for read. RS = logic 1
selects the data register for both read and write. There is
an internal pull-up on pin RS.
7.2
R/W: read/write (parallel control)
R/W selects either the read (R/W = logic 1) or write
(R/W = logic 0) operation when control is by the parallel
interface. There is an internal pull-up on this pin.
7.3
E: data bus clock
The E pin is set HIGH to signal the start of a read or write
operation when the device is controlled by the parallel
interface. Data is clocked in or out of the chip on the
negative edge of the clock. Note that this pin must be tied
to logic 0 (V
SS
) when I
2
C-bus control is used.
7.4
DB0 to DB7: data bus
The bidirectional, 3-state data bus transfers data between
the system controller and the PCF2116. DB7 may be used
as the Busy Flag, signalling that internal operations are not
yet completed. In 4-bit operations the 4 higher order lines
DB4 to DB7 are used; DB0 to DB3 must be left open
circuit. There is an internal pull-up on each of the data
lines. Note that these pins must be left open circuit when
I
2
C-bus control is used.
7.5
C1 to C60: column driver outputs
These pins output the data for pairs of columns.
This arrangement permits optimized chip-on-glass (COG)
layout for 4-line by 12 characters.
7.6
R1 to R32: row driver outputs
These pins output the row select waveforms to the left and
right halves of the display.
7.7
V
LCD
: LCD power supply
Negative power supply for the liquid crystal display.
This may be generated on-chip or supplied externally.
7.8
V
0
: V
LCD
control input
The input level at this pin determines the generated V
LCD
output voltage.
7.9
OSC: oscillator
When the on-chip oscillator is used this pin must be
connected to V
DD
. An external clock signal, if used, is input
at this pin.
7.10
SCL: serial clock line
Input for the I
2
C-bus clock signal.
7.11
SDA: serial data line
Input/output for the I
2
C-bus data line.
7.12
SA0: address pin
The hardware sub-address line is used to program the
device sub-address for 2 different PCF2116s on the same
I
2
C-bus.
7.13
T1: test pad
Must be connected to V
SS
. Not user accessible.
8
FUNCTIONAL DESCRIPTION
(see Fig.1)
8.1
LCD supply voltage generator, PCF2114x and
PCF2116x
The on-chip voltage generator is controlled by bit G of the
‘Function set’ instruction and V
0
.
V
0
is a high-impedance input and draws no current from
the system power supply. Its range is between V
SS
and
V
DD
1 V. When V
0
is connected to V
DD
the generator is
switched off and an external voltage must be supplied to
pin V
LCD
. This may be more negative than V
SS
.
When G = logic 1 the generator produces a negative
voltage at pin V
LCD
, controlled by the input voltage at
pin V
0
. The LCD operating voltage is given by the
relationship:
V
OP
= 1.8V
DD
V
0
Where:
V
OP
= V
DD
V
LCD
V
LCD
= V
0
(0.8V
DD
)
When G = logic 0, the generated output voltage V
LCD
is
equal to V
0
(between V
SS
and V
DD
). In this instance:
V
OP
= V
DD
V
0
When V
LCD
is generated on-chip the V
LCD
pin should be
decoupled to V
DD
with a suitable capacitor. V
DD
and V
0
must be selected to limit the maximum value of V
OP
to 9 V.
Figure 3 shows the two generator control characteristics.
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