1997 Apr 07
8
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
8.2
LCD supply voltage generator, PCF2116K
In the PCF2116K version, V
0
is connected through an
on-chip resistor (R
0
) to V
LCD
. Resistor R
0
has a nominal
value of 1 M
and draws a typical current of 4
μ
A from the
pin V
0
. A constant voltage (equal to 1.34V
DD
) is always
present across R
0
.
The voltage range of the PCF2116K is between V
SS
and
V
DD
0.5 V (see Fig.4). When V
0
is connected to V
DD
the
generator is switched off and an external voltage must be
supplied to pin V
LCD
. This may be more negative than V
SS
.
When G = logic 1 the generator produces a negative
voltage at pin V
LCD
, controlled by the input voltage at
pin V
0
. The LCD operating voltage is given by the
relationship:
V
OP
= 2.34V
DD
V
0
Where:
V
OP
= V
DD
V
LCD
V
LCD
= V
0
(1.34V
DD
)
When G = logic 0, the generated output voltage V
LCD
is
equal to V
0
(between V
SS
and V
DD
). In this instance:
V
OP
= V
DD
V
0
8.3
Character generator ROM (CGROM)
The standard character sets A, C and G are available for
the PCF2114x and PCF2116x. Standard character set C is
available for the PCF2116K.
8.4
LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system power consumption. The optimum levels depend
on the multiplex rate and are selected automatically when
the number of lines in the display is defined.
The optimum value of V
OP
depends on the multiplex rate,
the LCD threshold voltage (V
th
) and the number of bias
levels and is given by the relationships in Table 1.Using a
5-level bias scheme for 1 : 16 MUX rate allows V
OP
< 5 V
for most LCD liquids. The effect on the display contrast is
negligible.
8.5
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pin OSC must be connected to V
DD
.
8.6
External clock
If an external clock is to be used, it must be input at
pin OSC. The resulting display frame frequency is given by
f
frame
=
1
2304
f
osc
. A clock signal must always be present,
otherwise the LCD may be frozen in a DC state.
8.7
Power-on reset
The power-on reset block initializes the chip after
power-on or power failure.
8.8
Registers
The PCF2116 has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed.
The instruction register stores instruction codes such as
‘Display clear’ and ‘Cursor shift’, and address information
for the Display Data RAM (DDRAM) and Character
Generator RAM (CGRAM). The instruction register can be
written to, but not read, by the system controller.
The data register temporarily stores data to be read from
the DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM corresponding to the address in the
Address Counter is written to the data register prior to
being read by the ‘Read data’ instruction.
8.9
Busy Flag
The Busy Flag indicates the free/busy status of the
PCF2116. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output to pin DB7 when RS = logic 0 and R/W = logic 1.
Instructions should only be written after checking that the
Busy Flag is logic 0 or waiting for the required number of
clock cycles.
Table 1
Optimum values for V
OP
MUX RATE
NUMBER OF BIAS
LEVELS
V
OP
/V
th
DISCRIMINATION
V
on
/V
off
1.277
1.196
1 : 16
1 : 32
5
6
3.67
5.19